IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 85

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 5: Functional Description—ALTMEMPHY
PHY-to-Controller Interfaces
December 2010 Altera Corporation
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Figure 5–17
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With the AFI, high and low signals are combined in one signal, so for a single chip
select (ctl_cs_n) interface, ctl_cs_n[1:0], where location 0 appears on the
memory bus on one mem_clk cycle and location 1 on the next mem_clk cycle.
1
Word-aligned and word-unaligned reads and writes have the following
definitions:
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1
1
1
Spaced reads and writes have the following definitions:
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The burst length is four. A DDR2 SDRAM is used—the interface timing is identical
for DDR3 devices.
An 8-bit interface with one chip select.
The data for one controller clock (ctl_clk) cycle represents data for two memory
clock (mem_clk) cycles (half-rate interface).
Word-aligned for the single chip select is active (low) in location 1 (_l).
ctl_cs_n[1:0] = 01 when a write occurs. This alignment is the easiest
alignment to design with.
Word-unaligned is the opposite, so ctl_cs_n[1:0] = 10 when a read or write
occurs and the other control and data signals are distributed across consecutive
ctl_clk cycles.
Spaced writes—write commands separated by a gap of one controller clock
(ctl_clk) cycle
Spaced reads—read commands separated by a gap of one controller clock
(ctl_clk) cycle
This convention is maintained for all signals so for an 8 bit memory
interface, the write data (ctl_wdata) signal is ctl_wdata[31:0], where the
first data on the DQ pins is ctl_wdata[7:0], then ctl_wdata[15:8], then
ctl_wdata[23:16], then ctl_wdata[31:24].
The Altera high-performance controllers use word-aligned data only.
The timing analysis script does not support word-unaligned reads and
writes.
Word-unaligned reads and writes are only supported on Stratix III and
Stratix IV devices.
through
Figure 5–20
assume the following general points:
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
External Memory Interface Handbook Volume 3
5–33