IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 27

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 2: Getting Started
HardCopy Device Migration Guidelines
December 2010 Altera Corporation
1
Table 2–7. PHY Sequencer Parameters (Part 2 of 2)
The sequencer in this example is set up to operate with 40 PLL phase steps per clock
cycle. (This information appears in the message panel of the ALTMEMPHY parameter
editor during generation of the IP core.)
Compiling Your Design for a Faster Speed Grade FPGA
The ALTMEMPHY parameter editor generates PLL parameters that match the PHY
requirement that the minimum PLL phase step size be one-eighth of the nominal VCO
operating period. In a C2 speed grade FPGA, the VCO is configured to run at
1515 MHz with an associated phase step of 82 ps.
PLL parameters. As shown, the PLL setup produces 40 phase steps per memory clock
cycle, matching the sequencer setup. This analysis, however, does not apply when
you select a HardCopy device.
Table 2–8. Generated PLL Parameters for a C2 speed grade FPGA
The HardCopy flow targets the center of the silicon process; therefore, all hard IP
blocks within the prototype FPGA must be configured accordingly to guarantee
functional equivalency. When a HardCopy device is selected, the Quartus II Fitter
restricts the operating range of the PLL to match the HardCopy silicon capability,
regardless of the speed grade of the selected FPGA. This restriction can alter the final
configuration of the PLL, producing a mismatch between the generated sequencer
setup stored in RTL, and the PLL behavior generated by the Quartus II Fitter.
Table 2–9
regardless of the chosen FPGA speed grade.
Table 2–9. Post-fit PLL Parameters When Using a HardCopy Device
PLL_STEPS_PER_CYCLE
MEM_IF_ADDR_CMD_PHASE
VCO OPERATING FREQUENCY
VCO PHASE SHIFT STEP
MEMORY CLOCK PERIOD
PLL PHASE STEPS PER MEMCLK PERIOD
VCO OPERATING FREQUENCY
VCO PHASE SHIFT STEP
MEMORY CLOCK PERIOD
PLL PHASE STEPS PER MEMCLK PERIOD
summarizes the post-fit PLL setup when HardCopy migration is selected,
Parameter
Parameter
Parameter
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
40
240
1515 MHz
82 ps
3300 ps
40
1212.1 MHz
103 ps
3300 ps
32
Table 2–8
External Memory Interface Handbook Volume 3
summarizes the generated
Setting
Setting
Setting
2–11