IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 108
![IP CORE Renewal Of IP-HPMCII](/photos/24/19/241941/4696148_sml.jpg)
IPR-HPMCII
Manufacturer Part Number
IPR-HPMCII
Description
IP CORE Renewal Of IP-HPMCII
Manufacturer
Altera
Datasheet
1.IP-HPMCII.pdf
(176 pages)
Specifications of IPR-HPMCII
Software Application
IP CORE, Memory Controllers, SDRAM
Supported Families
Arria II GX, HardCopy III, Stratix III, Stratix IV
Core Architecture
FPGA
Core Sub-architecture
Arria, HardCopy, Stratix
Rohs Compliant
NA
Lead Free Status / RoHS Status
na
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6–14
Example Top-Level File
Figure 6–6. Testbench and Example Top-Level File
Table 6–10. Example Top-Level File and Testbench Files
External Memory Interface Handbook Volume 3
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
<variation name>_example_top_tb.v or .vhd
<variation name>_example_top.v or .vhd
<variation name>_mem_model.v or .vhd
<variation name>_full_mem_model.v or .vhd
<variation name>_example_driver.v or .vhd
<variation name> .v or .vhd
<variation name>.qip
test_complete
clock_source
pnf
Table 6–9
Table 6–9. Double-Bit Error Location Status Register
The MegaWizard Plug-In Manager helps you create an example top-level file that
shows you how to instantiate and connect the DDR3 SDRAM HPC. The example
top-level file consists of the DDR3 HPC, some driver logic to issue read and write
requests to the controller. The example top-level file is a working system that you can
compile and use for both static timing checks and board tests.
Figure 6–6
Table 6–10
the testbench.
Bits N-1 down to 0
Others
Filename
Testbench
Example Design
Example Driver
shows the double-bit error location status register.
shows the testbench and the example top-level file.
describes the files that are associated with the example top-level file and
Bit
Cause of Interrupt
Reserved
DDR3 SDRAM Controller
Control
Logic
Testbench for the example top-level file.
Example top-level file.
Associative-array memory model.
Full-array memory model.
Example driver.
Top-level description of the custom MegaCore function.
Contains Quartus II project information for your MegaCore
function variations.
Name
Chapter 6: Functional Description—High-Performance Controller
ALTMEMPHY
DLL
PLL
When 0, no double-bit error; when 1,
double-bit error occurred in this 64-bit part.
Reserved.
Description
December 2010 Altera Corporation
Description
Memory Model
Generated
Wizard-
Example Top-Level File
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