IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 130

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

7–14
Table 7–5. Local Interface Signals (Part 1 of 3)
External Memory Interface Handbook Volume 3
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
local_address[]
local_be[]
local_burstbegin
Signal Name
Table 7–5
Direction
shows the DD3 SDRAM HPC II local interface signals.
Input
Input
Input
Memory address at which the burst should start.
By default, the local address is mapped to the bank interleaving scheme. You
can change the ordering via the Local-to-Memory Address Mapping option
in the Controller Settings page.
The width of this bus is sized using the following equation:
For one chip select:
width = row bits + bank bits + column bits – 2
For multiple chip selects:
width = chip bits + row bits + bank bits + column bits – 2
If the bank address is 2 bits wide, row is 13 bits wide and column is 10 bits
wide, then the local address is 23 bits wide. To map local_address to
bank, row and column address:
local_address is 23 bits wide
local_address[22:10] = row address[12:0]
local_address[9:8] = bank address [1:0]
local_address [7:0] = column address[9:2]
Two least significant bits (LSB) of the column address on the memory side
are ignored, because the local data width is four times that of the memory
data bus width.
Byte enable signal, which you use to mask off individual bytes during writes.
local_be is active high; mem_dm is active low.
To map local_wdata and local_be to mem_dq and mem_dm, consider a
full-rate design with 32-bit local_wdata and 16-bit mem_dq.
Local_wdata = < 22334455 >< 667788AA >< BBCCDDEE >
Local_be
These values map to:
Mem_dq = <4455><2233><88AA><6677><DDEE><BBCC>
Mem_dm = <1 1 ><0 0 ><0 1 ><1 0 ><0 1 ><0 1 >
Avalon burst begin strobe, which indicates the beginning of an Avalon burst.
Unlike all other Avalon-MM signals, the burst begin signal does not stay
asserted if local_ready is deasserted.
For write transactions, assert this signal at the beginning of each burst
transfer and keep this signal high for one cycle per burst transfer, even if the
slave has deasserted the local_ready signal. This signal is sampled at the
rising edge of the phy_clk when the local_write_req signal is asserted.
After the slave deasserts the local_ready signal, the master keeps all the
write request signals asserted until local_ready signal becomes high
again.
For read transactions, assert this signal for one clock cycle when read
request is asserted and the local_address from which the data should be
read is given to the memory. After the slave deasserts the local_ready
signal (waitrequest_n in Avalon interface), the master keeps all the read
request signals asserted until the local_ready signal becomes high again.
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Chapter 7: Functional Description—High-Performance Controller II
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Description
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December 2010 Altera Corporation
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Top-level Signals Description
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