DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 473

MCU 3V 64K 100-TQFP

DF2110BVTE10

Manufacturer Part Number
DF2110BVTE10
Description
MCU 3V 64K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2110BVTE10

Core Processor
H8S/2000
Core Size
16-Bit
Speed
10MHz
Connectivity
Host Interface (LPC), I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
82
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Other names
HD64F2110BVTE10
HD64F2110BVTE10

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2110BVTE10V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
This LSI incorporates a clock pulse generator, which generates the system clock ( ), bus master
clock, and internal clock.
The clock pulse generator consists of an oscillator, duty correction circuit, clock select circuit,
medium-speed clock divider, bus master clock select circuit, subclock input circuit, and waveform
forming circuit. Figure 18.1 shows a block diagram of the clock pulse generator.
The bus master clock is selected as either high-speed mode or medium-speed mode by software
according to the settings of the SCK2 to SCK0 bits in the standby control register. For details on
the standby control register, refer to section 19.1.1, Standby Control Register (SBYCR).
The subclock input is controlled by software according to the EXCLE bit setting in the low power
control register. For details on the low power control register, refer to section 19.1.2, Low Power
Control Register (LPWRCR).
EXTAL
XTAL
EXCL
input circuit
Subclock
Oscillator
Figure 18.1 Block Diagram of Clock Pulse Generator
Section 18 Clock Pulse Generator
Waveform
correction
forming
circuit
circuit
Duty
count clock
φSUB
WDT_1
Clock select
circuit
System clock
to φ pin
Rev. 2.00 Mar 21, 2006 page 433 of 518
speed clock
Medium-
divider
Section 18 Clock Pulse Generator
Internal clock
to peripheral
modules
φ/2
to φ/32
φ
clock select
Bus master
circuit
REJ09B0299-0200
Bus master clock
to CPU

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