DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 407

MCU 3V 64K 100-TQFP

DF2110BVTE10

Manufacturer Part Number
DF2110BVTE10
Description
MCU 3V 64K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2110BVTE10

Core Processor
H8S/2000
Core Size
16-Bit
Speed
10MHz
Connectivity
Host Interface (LPC), I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
82
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Other names
HD64F2110BVTE10
HD64F2110BVTE10

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2110BVTE10V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Bit
4
3
2
1
Bit Name Initial Value Slave Host Description
LRSTB
SDWNB
PMEB
LSMIB
0
0
0
0
R/W
R/W
R/W
R/W
LPC Software Reset Bit
Resets the host interface. For the scope of
initialization by an LPC reset, see section 15.4.4,
Host Interface Shutdown Function (LPCPD).
0: Normal state
[Clearing conditions]
1: LPC software reset state
[Setting condition]
Writing 1 after reading LRSTB = 0
LPC Software Shutdown Bit
Controls host interface shutdown. For details of the
LPC shutdown function, and the scope of
initialization by an LPC reset and an LPC shutdown,
see section 15.4.4, Host Interface Shutdown
Function (LPCPD).
0: Normal state
[Clearing conditions]
1: LPC software shutdown state
[Setting condition]
Writing 1 after reading SDWNB = 0
PME Output Bit
Controls PME output in combination with the PMEE
bit. For details, refer to description on the PMEE bit
in HICR0.
LSMI Output Bit
Controls LSMI output in combination with the LSMIE
bit. For details, refer to description on the LSMIE bit
in HICR0.
Writing 0
LPC hardware reset
Writing 0
LPC hardware reset or LPC software reset
LPC hardware shutdown
LPC hardware shutdown release
(rising edge of LPCPD signal when SDWNE = 0)
Section 15 Host Interface LPC Interface (LPC)
Rev. 2.00 Mar 21, 2006 page 367 of 518
REJ09B0299-0200

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