DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 32

• Manufacturer Part Number: DF2110BVTE10
• Description: MCU 3V 64K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2110BVTE10

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: Host Interface (LPC), I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: HD64F2110BVTE10; HD64F2110BVTE10

Figure 12.8
Figure 12.9
Figure 12.9
Figure 12.10 Example of Communication Using Multiprocessor Format
Figure 12.11 Sample Multiprocessor Serial Transmission Flowchart....................................... 250
Figure 12.12 Example of SCI Receive Operation (Example with 8-Bit Data,
Figure 12.13 Sample Multiprocessor Serial Reception Flowchart (1) ...................................... 252
Figure 12.13 Sample Multiprocessor Serial Reception Flowchart (2) ...................................... 253
Figure 12.14 Data Format in Clocked Synchronous Communication (LSB-First) ................... 254
Figure 12.15 Sample SCI Initialization Flowchart.................................................................... 255
Figure 12.16 Example of SCI Transmit Operation in Clocked Synchronous Mode ................. 256
Figure 12.17 Sample Serial Transmission Flowchart................................................................ 257
Figure 12.18 Example of SCI Receive Operation in Clocked Synchronous Mode................... 258
Figure 12.19 Sample Serial Reception Flowchart ..................................................................... 259
Figure 12.20 Sample Flowchart of Simultaneous Serial Transmission and Reception ............. 261
Figure 12.21 Sample Flowchart for Mode Transition during Transmission ............................. 265
Figure 12.22 Pin States during Transmission in Asynchronous Mode (Internal Clock) ........... 265
Figure 12.23 Pin States during Transmission in Clocked Synchronous Mode
Figure 12.24 Sample Flowchart for Mode Transition during Reception................................... 266
Figure 12.25 Switching from SCK Pins to Port Pins ................................................................ 267
Figure 12.26 Prevention of Low Pulse Output at Switching from SCK Pins to Port Pins ........ 267
Section 13 I
Figure 13.1
Figure 13.2
Figure 13.3
Figure 13.4
Figure 13.5
Figure 13.6
Figure 13.7
Figure 13.8
Figure 13.9
Figure 13.10 Sample Flowchart for Operations in Master Receive Mode (HNDS = 1) ........... 304
Figure 13.11 Example of Operation Timing in Master Receive Mode (MLS = WAIT = 0,
Rev. 2.00 Mar 21, 2006 page xxx of xxxviii
2
C Bus Interface (IIC)
Example of SCI Receive Operation in Asynchronous Mode
(Example with 8-Bit Data, Parity, One Stop Bit)................................................. 244
Sample Serial Reception Flowchart (1) ............................................................... 246
Sample Serial Reception Flowchart (2) ............................................................... 247
(Transmission of Data H'AA to Receiving Station A)......................................... 249
Multiprocessor Bit, One Stop Bit) ....................................................................... 251
(Internal Clock).................................................................................................... 266
Block Diagram of I
I
I
I
I
Sample Flowchart for IIC Initialization ............................................................... 299
Sample Flowchart for Operations in Master Transmit Mode............................... 300
Example of Operation Timing in Master Transmit Mode (MLS = WAIT = 0) ... 302
Example of Stop Condition Issuance Operation Timing in Master
Transmit Mode (MLS = WAIT = 0) .................................................................... 303
HNDS = 1) ........................................................................................................... 306
2
2
2
2
C Bus Interface Connections (Example: This LSI as Master) ........................... 272
C Bus Data Format (I
C Bus Data Format (Serial Format)................................................................... 297
C Bus Timing .................................................................................................... 298
2
C Bus Interface .................................................................... 271
2
C Bus Format) ................................................................ 297