DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 411

• Manufacturer Part Number: DF2110BVTE10
• Description: MCU 3V 64K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2110BVTE10

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: Host Interface (LPC), I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: HD64F2110BVTE10; HD64F2110BVTE10

15.3.3
LADR3 comprises two 8-bit readable/writable registers that perform LPC channel-3 host address
setting and control the operation of the bidirectional data registers. The contents of the address
field in LADR3 must not be changed while channel 3 is operating (while LPC3E is set to 1).
Bit
7
6
5
4
3
2
1
0
Bit
7
6
5
4
3
2
1
0
LADR3H
LADR3L
Bit Name Initial Value R/W
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit Name Initial Value R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 1
TWRE
LPC Channel 3 Address Register (LADR3)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Channel 3 Address Bits 15 to 8:
When LPC3E = 1, an I/O address received in an LPC I/O
cycle is compared with the contents of LADR3. When
determining an IDR3, ODR3, or STR3 address match, bit 0
of LADR3 is regarded as 0, and the value of bit 2 is ignored.
When determining a TWR0 to TWR15 address match, bit 4
of LADR3 is inverted, and the values of bits 3 to 0 are
ignored. Register selection according to the bits ignored in
address match determination is as shown in table 15.2.
Description
Channel 3 Address Bits 7 to 3
Reserved
This bit is readable/writable, however, only 0 should be
written to this bit.
Channel 3 Address Bit 1
Bidirectional Data Register Enable
Enables or disables bidirectional data register operation.
0: TWR operation is disabled
TWR-related I/O address match determination is halted
1: TWR operation is enabled
Section 15 Host Interface LPC Interface (LPC)
Rev. 2.00 Mar 21, 2006 page 371 of 518
REJ09B0299-0200