DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 468

MCU 3V 64K 100-TQFP

DF2110BVTE10

Manufacturer Part Number
DF2110BVTE10
Description
MCU 3V 64K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2110BVTE10

Core Processor
H8S/2000
Core Size
16-Bit
Speed
10MHz
Connectivity
Host Interface (LPC), I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
82
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Other names
HD64F2110BVTE10
HD64F2110BVTE10

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2110BVTE10V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 17 ROM
Rev. 2.00 Mar 21, 2006 page 428 of 518
REJ09B0299-0200
Notes: 1. Prewriting (writing 0 to all data in erased block) is not necessary.
2. The values of x, y, z, , ,
3. Verify data is read in 16-bit (word) units.
4. Set only a single bit in EBR1 and EBR2. Do not set more than one bit.
5. Erasing is performed in block units. To erase multiple blocks, each block must be erased in turn.
Increment
address
Figure 17.10 Erase/Erase-Verify Flowchart
NG
NG
H'FF dummy write to verify address
, , , and N are shown in section 21.1.4, Flash Memory Characteristics.
Clear ESU bit in FLMCR2
Clear SWE bit in FLMCR1
Set SWE bit in FLMCR1
*
All erase blocks erased?
Set ESU bit in FLMCR2
Set block start address
Clear EV bit in FLMCR1
Clear E bit in FLMCR1
Set EV bit in FLMCR1
5
Set EBR1 and EBR2
Set E bit in FLMCR1
as verify address
Read verify data
End of erasing
Disable WDT
Enable WDT
Last address
Wait ( z ) ms
Wait ( ) s
Wait ( x ) s
Wait ( y ) s
Wait ( ) s
Wait ( ) s
Wait ( ) s
Wait ( ) s
Verify data
Wait ( ) s
= all "1"?
of block?
START
n = 1
OK
OK
OK
*
1
NG
*
2
Start of erasing
End of erasing
*
*
*
*
*
*
*
*
*
2
4
2
2
2
2
2
2
3
Clear SWE bit in FLMCR1
Clear EV bit in FLMCR1
Wait ( ) s
Wait ( ) s
Erase failure
n ( N ) ?
OK
*
2
NG
*
n
2
n + 1

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