DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 39

• Manufacturer Part Number: DF2110BVTE10
• Description: MCU 3V 64K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2110BVTE10

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: Host Interface (LPC), I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: HD64F2110BVTE10; HD64F2110BVTE10

Section 17 ROM
Table 17.1
Table 17.2
Table 17.3
Table 17.4
Table 17.5
Table 17.6
Section 18 Clock Pulse Generator
Table 18.1
Table 18.2
Table 18.3
Table 18.4
Table 18.5
Section 19 Power-Down Modes
Table 19.1
Table 19.2
Section 21 Electrical Characteristics
Table 21.1
Table 21.2
Table 21.2
Table 21.2
Table 21.3
Table 21.4
Table 21.5
Table 21.6
Table 21.7
Table 21.8
Table 21.9
Table 21.10 LPC Module Timing .............................................................................................. 498
Table 21.11 Flash Memory Characteristics................................................................................ 499
Appendix A I/O Port States in Each Processing State
Table A.1
Differences between Boot Mode and User Program Mode.................................... 411
Pin Configuration ................................................................................................... 415
Operating Modes and ROM ................................................................................... 419
On-Board Programming Mode Settings................................................................. 419
Boot Mode Operation............................................................................................. 422
System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate
Is Possible............................................................................................................... 423
Damping Resistance Values ................................................................................... 434
Crystal Resonator Parameters ................................................................................ 435
External Clock Input Conditions ............................................................................ 436
External Clock Output Stabilization Delay Time................................................... 437
Subclock Input Conditions ..................................................................................... 438
Operating Frequency and Wait Time ..................................................................... 443
LSI Internal States in Each Operating Mode.......................................................... 448
Absolute Maximum Ratings................................................................................... 487
DC Characteristics (1) ............................................................................................ 488
DC Characteristics (2) ............................................................................................ 490
DC Characteristics (3) When LPC Function Is Used ............................................. 491
Permissible Output Currents .................................................................................. 491
Bus Drive Characteristics ....................................................................................... 493
Clock Timing ......................................................................................................... 494
Control Signal Timing............................................................................................ 495
Timing of On-Chip Peripheral Modules................................................................. 496
Keyboard Buffer Controller Timing....................................................................... 497
I
I/O Port States in Each Processing State ................................................................ 511
2
C Bus Timing....................................................................................................... 497
Rev. 2.00 Mar 21, 2006 page xxxvii of xxxviii