DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 339

• Manufacturer Part Number: DF2110BVTE10
• Description: MCU 3V 64K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2110BVTE10

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: Host Interface (LPC), I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: HD64F2110BVTE10; HD64F2110BVTE10

13.4.2
Initialize the IIC by the procedure shown in figure 13.6 before starting transmission/reception of
data.
Note:
If the ICMR register is modified during transmit/receive operation, bit counter BC2 to BC0 will be
modified erroneously, thus causing incorrect operation.
13.4.3
In I
data, and the slave device returns an acknowledge signal.
Figure 13.7 shows the sample flowchart for the operations in master transmit mode.
2
C bus format master transmit mode, the master device outputs the transmit clock and transmit
<< Start transmit/receive operation >>
Be sure to modify the ICMR register after transmit/receive operation has been completed.
Initialization
Master Transmit Operation
Set MSTP4 = 0 (IIC_0)
Set IICE = 1 in STCR
Set ICE = 0 in ICCR
Set ICE = 1 in ICCR
Set SAR and SARX
MSTP3 = 0 (IIC_1)
Start initialization
(MSTPCRL)
Set STCR
Set ICMR
Set ICSR
Set ICXR
Set ICCR
Figure 13.6 Sample Flowchart for IIC Initialization
Cancel module stop mode
Enable the CPU accessing to the IIC control register and data register
Enable SAR and SARX to be accessed
Set the first and second slave addresses and IIC communication format
(SVA6 to SVA0, FS, SVAX6 to SVAX0, and FSX)
Enable ICMR and ICDR to be accessed
Use SCL/SDA pin as an IIC port
Set acknowledge bit (ACKB)
Set transfer rate (IICX)
Set communication format, wait insertion, and transfer rate
(MLS, WAIT, CKS2 to CKS0)
Enable interrupt
(STOPIM, HNDS, ALIE, ALSL, FNC1, and FNC0)
Set interrupt enable, transfer mode, and acknowledge decision
(IEIC, MST, TRS, and ACKE)
Rev. 2.00 Mar 21, 2006 page 299 of 518
Section 13 I
2
C Bus Interface (IIC)
REJ09B0299-0200