DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 443

• Manufacturer Part Number: DF2110BVTE10
• Description: MCU 3V 64K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2110BVTE10

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: Host Interface (LPC), I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: HD64F2110BVTE10; HD64F2110BVTE10

15.5
15.5.1
The host interface has four interrupt requests for the slave processor (this LSI): IBF1 to IBF3, and
ERRI. IBFI1 to IBFI3 are IDR receive complete interrupts for IDR1 to IDR3 and TWR,
respectively. The ERRI interrupt indicates the occurrence of a special state such as an LPC reset,
LPC shutdown, or transfer cycle abort. An interrupt request is enabled by setting the
corresponding enable bit.
Table 15.8 Receive Complete Interrupts and Error Interrupt
Interrupt
IBFI1
IBFI2
IBFI3
ERRI
15.5.2
The host interface can request seven kinds of host interrupt by means of SERIRQ. HIRQ1 and
HIRQ12 are used on LPC channel 1 only, while SMI, HIRQ6, HIRQ9 to HIRQ11 can be
requested from LPC channel 2 or 3.
There are two ways of clearing a host interrupt request.
When the IEDIR bit is cleared to 0 in SIRQCR0, host interrupt sources and LPC channels are all
linked to the host interrupt request enable bits. When the OBF flag is cleared to 0 by a read of
ODR or TWR15 by the host in the corresponding LPC channel, the corresponding host interrupt
enable bit is automatically cleared to 0, and the host interrupt request is cleared.
When the IEDIR bit is set to 1 in SIRQCR0, LPC channel 2 and 3 interrupt requests are dependent
only upon the host interrupt enable bits. The host interrupt enable bit is not cleared when OBF for
channel 2 or 3 is cleared. Therefore, SMIE2, SMIE3A and SMIE3B, IRQ6E2 and IRQ6E3,
IRQ9E2 and IRQ9E3, IRQ10E2 and IRQ10E3, and IRQ11E2 and IRQ11E3 lose their respective
functional differences. In order to clear a host interrupt request, it is necessary to clear the host
interrupt enable bit.
IBFI1, IBFI2, IBFI3, and ERRI
SMI, HIRQ1, HIRQ6, HIRQ9, HIRQ10, HIRQ11, and HIRQ12
Interrupt Sources
Description
When IBFIE1 is set to 1 and IDR1 reception is completed
When IBFIE2 is set to 1 and IDR2 reception is completed
When IBFIE3 is set to 1 and IDR3 reception is completed, or when TWRE and
IBFIE3 are set to 1 and reception is completed up to TWR15
When ERRIE is set to 1 and one of LRST, SDWN and ABRT is set to 1
Section 15 Host Interface LPC Interface (LPC)
Rev. 2.00 Mar 21, 2006 page 403 of 518
REJ09B0299-0200