DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 347

• Manufacturer Part Number: DF2110BVTE10
• Description: MCU 3V 64K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2110BVTE10

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: Host Interface (LPC), I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: HD64F2110BVTE10; HD64F2110BVTE10

Figure 13.13 Sample Flowchart for Operations in Master Receive Mode
No
No
No
Set BBSY = 0 and SCP = 0
Wait for one clock pulse
Clear IRIC flag in ICCR
Clear IRIC flag in ICCR
Clear IRIC flag in ICCR
Set HNDS = 0 in ICXR
Set ACKB = 0 in ICSR
Clear IRIC flag in ICCR
Set WAIT = 1 in ICMR
Read IRIC flag in ICCR
Set ACKB = 1 in ICSR
Clear IRIC flag in ICCR
Read IRIC flag in ICCR
Set WAIT = 0 in ICMR
Set TRS = 0 in ICCR
Master receive mode
Set TRS = 1 in ICCR
(Receiving Multiple Bytes) (WAIT = 1)
Last receive?
Read ICDR
Read ICDR
Read ICDR
Read ICDR
IRTR = 1?
IRTR = 1?
IRIC = 1?
IRIC = 1?
in ICCR
End
Yes
Yes
Yes
No
No
Yes
Yes
[16] Read the last receive data.
[17] Generate stop condition
[1] Select receive mode.
[2] Start receiving. The first read
[3] Wait for a receive wait
[5] Read the receive data.
[6] Clear IRIC flag.
[7] Set acknowledge data for the last reception.
[8] Wait for TRS setting
[9] Set TRS for stop condition issuance
[10] Read the receive data.
[11] Clear IRIC flag. (to end the wait insertion)
[12] Wait for a receive wait
[13] Determine end of reception
[14] Clear IRIC.
[15] Clear wait mode.
[4] Determine end of reception
(Set IRIC at the fall of the 8th clock) or,
Wait for 1 byte to be received
(Set IRIC at the rise of the 9th clock)
(Set IRIC at the fall of the 8th clock) or,
Wait for 1 byte to be received
(Set IRIC at the rise of the 9th clock)
is a dummy read.
(to end the wait insertion)
(to end the wait insertion)
Clear IRIC flag.
( IRIC flag should be cleared to 0
after setting WAIT = 0.)
Rev. 2.00 Mar 21, 2006 page 307 of 518
Section 13 I
2
C Bus Interface (IIC)
REJ09B0299-0200