DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 114

MCU 3V 64K 100-TQFP

DF2110BVTE10

Manufacturer Part Number
DF2110BVTE10
Description
MCU 3V 64K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2110BVTE10

Core Processor
H8S/2000
Core Size
16-Bit
Speed
10MHz
Connectivity
Host Interface (LPC), I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
82
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Other names
HD64F2110BVTE10
HD64F2110BVTE10

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2110BVTE10V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 5 Interrupt Controller
When pin IRQ6 is used as an IRQ6 interrupt input pin, clear the KMIMR6 bit to 0.
When pin IRQ7 is used as an IRQ7 interrupt pin, set all of bits KMIMR15 to KMIMR8 and
WUEMR7 to WUEMR0 to 1. If any of these bits is cleared to 0, IRQ7 interrupt input from the
IRQ7 pin will be ignored.
Since interrupt request flags IRQ7F to IRQ0F are set each time the setting condition is satisfied,
regardless of the IER setting, refer to a needed flag only.
KIN15 to KIN0 Interrupts, WUE7 to WUE0 Interrupts: Interrupts KIN15 to KIN0 and WUE7
to WUE0 are requested by an input signal at pins KIN15 to KIN0 and WUE7 to WUE0. When
pins KIN15 to KIN0 and WUE7 to WUE0 are used for key-sense input or wakeup event, clear the
corresponding KMIMR and WUEMR bits to 0 in order to enable their key-sense input and
wakeup event interrupts. Remaining unused KMIMR and WUEMR bits for key-sense input
should be set to 1 in order to disable interrupts. Interrupts WUE7 to WUE0 and KIN15 to KIN8
generate IRQ7 interrupts, and interrupts KIN7 to KIN0 generate IRQ6 interrupts. The pin
conditions for interrupt request generation, enable of interrupt requests, settings of interrupt
control levels, and status display of interrupt requests depend on each setting and display of the
IRQ7 or IRQ6 interrupt.
When pins KIN7 to KIN0, KIN15 to KIN8, or WUE7 to WUE0 are used as key-sense interrupt
input pins or wakeup event interrupt input pins, either low-level sensing or falling-edge sensing
must be designated as the interrupt sense condition for the corresponding interrupt source (IRQ6
or IRQ7).
5.4.2
Internal interrupts issued from the on-chip peripheral modules have the following features:
1. For each on-chip peripheral module there are flags that indicate the interrupt request status,
2. The control level for each interrupt can be set by ICR.
5.5
Table 5.3 lists interrupt exception handling sources, vector addresses, and interrupt priorities. For
default priorities, the lower the vector number, the higher the priority. Modules set at the same
priority will conform to their default priorities. Priorities within a module are fixed.
Rev. 2.00 Mar 21, 2006 page 74 of 518
REJ09B0299-0200
and enable bits that individually select enabling or disabling of these interrupts. When the
enable bit for a particular interrupt source is set to 1, an interrupt request is sent to the interrupt
controller.
Internal Interrupts
Interrupt Exception Handling Vector Table

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