DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 436

• Manufacturer Part Number: DF2110BVTE10
• Description: MCU 3V 64K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2110BVTE10

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: Host Interface (LPC), I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: HD64F2110BVTE10; HD64F2110BVTE10

Section 15 Host Interface LPC Interface (LPC)
15.4.4
The host interface can be placed in the shutdown state according to the state of the LPCPD pin.
There are two kinds of host interface shutdown state: LPC hardware shutdown and LPC software
shutdown. The LPC hardware shutdown state is controlled by the LPCPD pin, while the software
shutdown state is controlled by the SDWNB bit. In both states, the host interface enters the reset
state by itself, and is no longer affected by external signals other than the LRESET and LPCPD
signals.
Placing the slave processor in sleep mode or software standby mode is effective in reducing
current dissipation in the shutdown state. If software standby mode is set, some means must be
provided for exiting software standby mode before clearing the shutdown state with the LPCPD
signal.
If the SDWNE bit has been set to 1 beforehand, the LPC hardware shutdown state is entered at the
same time as the LPCPD signal falls, and prior preparation is not possible. If the LPC software
shutdown state is set by means of the SDWNB bit, on the other hand, the LPC software shutdown
state cannot be cleared at the same time as the rise of the LPCPD signal. Taking these points into
consideration, the following operating procedure uses a combination of LPC software shutdown
and LPC hardware shutdown.
1. Clear the SDWNE bit to 0.
2. Set the ERRIE bit to 1 and wait for an interrupt by the SDWN flag.
3. When an ERRI interrupt is generated by the SDWN flag, check the host interface internal
4. Set the SDWNB bit to 1 to set LPC software standby mode.
5. Set the SDWNE bit to 1 and make a transition to LPC hardware standby mode. The SDWNB
6. Check the state of the LPCPD signal to make sure that the LPCPD signal has not risen during
7. Place the slave processor in sleep mode or software standby mode as necessary.
8. If software standby mode has been set, exit software standby mode by some means
9. When a rising edge is detected in the LPCPD signal, the SDWNE bit is automatically cleared
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status flags and perform any necessary processing.
bit is cleared automatically.
steps 3 to 5. If the signal has risen, clear SDWNE to 0 to return to the state in step 1.
independent of the LPC.
to 0. If the slave processor has been placed in sleep mode, the mode is exited by means of
LRESET signal input, on completion of the LPC transfer cycle, or by some other means.
Host Interface Shutdown Function (LPCPD)