DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 168

• Manufacturer Part Number: DF2110BVTE10
• Description: MCU 3V 64K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2110BVTE10

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: Host Interface (LPC), I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: HD64F2110BVTE10; HD64F2110BVTE10

Section 7 I/O Ports
7.12.3
PBPIN indicates the port B state.
Bit
7
6
5
4
3
2
1
0
Note: * The initial value is determined according to the PB7 to PB0 pin states.
7.12.4
PBnDDR
Pin Function
Note: * This pin can always be used as the WUEn input pin. (n = 7 to 2)
LSCIE
HI12E
PB1DDR
Pin Function
Notes: 1. When bit LSCIE is set to 1 in HICR0, bits HI12E and PB1DDR should be cleared to 0.
Rev. 2.00 Mar 21, 2006 page 128 of 518
REJ09B0299-0200
PB7/WUE7, PB6/WUE6, PB5/WUE5, PB4/WUE4, PB3/WUE3, PB2/WUE2
The pin function is switched as shown below according to the status of the PBnDDR bit.
PB1/WUE1/LSCI
The pin function is switched as shown below according to the combination of the HI12E bit in
SYSCR2, the LSCIE bits in HICR0 of host interface (LPC), and the PB1DDR bit.
2. This pin can always be used as the WUE1 or LSCI input pin.
Bit Name
PB7PIN
PB6PIN
PB5PIN
PB4PIN
PB3PIN
PB2PIN
PB1PIN
PB0PIN
Port B Input Data Register (PBPIN)
Pin Functions
Initial Value
Undefined *
Undefined *
Undefined *
Undefined *
Undefined *
Undefined *
Undefined *
Undefined *
PB1input pin
0
PBn input pin
R
R
R
R
R
R
R
R
R/W
0
WUE1 input pin *
Description
Reading PBPIN always returns the pin states.
PBPIN has the same address as P8DDR. If a write
is performed, data will be written to P8DDR and
the port 8 settings will change.
0
0
WUEn input pin *
PB1 output pin
1
2
, LSCI input pin *
PBn output pin
2
LSCI output pin
1
0 *
0 *
1
1
1