DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 162

• Manufacturer Part Number: DF2110BVTE10
• Description: MCU 3V 64K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2110BVTE10

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: Host Interface (LPC), I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: HD64F2110BVTE10; HD64F2110BVTE10

Section 7 I/O Ports
P90DDR
Pin Function
Note: * When the IRQ2E bit in IER is set to 1, this pin is used as the IRQ2 input pin.
7.11
Port A is an 8-bit I/O port. Port A pins also function as keyboard buffer controller I/O pins, and
key-sense interrupt input pins. Port A input/output operates by VccB power independent from the
Vcc power. Up to 5 V can be applied to port A pins if VccB power is 5 V. Port A has the
following registers. PADDR and PAPIN have the same address.
7.11.1
PADDR specifies input or output for the pins of port A on a bit-by-bit basis.
Bit
7
6
5
4
3
2
1
0
Rev. 2.00 Mar 21, 2006 page 122 of 518
REJ09B0299-0200
P90/IRQ2
The pin function is switched as shown below according to the status of the P90DDR bit.
Port A data direction register (PADDR)
Port A output data register (PAODR)
Port A input data register (PAPIN)
Bit Name
PA7DDR
PA6DDR
PA5DDR
PA4DDR
PA3DDR
PA2DDR
PA1DDR
PA0DDR
Port A
Port A Data Direction Register (PADDR)
Initial Value
0
0
0
0
0
0
0
0
P90 input pin
W
W
W
W
W
W
W
W
R/W
0
Description
The corresponding port A pins are output ports
when PADDR bits are set to 1, and input ports
when cleared to 0.
PA7 to PA2 pins are used as the keyboard buffer
controller I/O pins by setting the KBIOE bit to 1,
while the I/O direction according to PA7DDR to
PA2DDR is ignored.
PADDR has the same address as PAPIN, if read,
port A status is returned.
IRQ2 input pin *
P90 output pin
1