DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 323
DF2110BVTE10
Manufacturer Part Number
DF2110BVTE10
Description
MCU 3V 64K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.DF2110BVTE10V.pdf
(561 pages)
Specifications of DF2110BVTE10
Core Processor
H8S/2000
Core Size
16-Bit
Speed
10MHz
Connectivity
Host Interface (LPC), I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
82
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Other names
HD64F2110BVTE10
HD64F2110BVTE10
HD64F2110BVTE10
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2110BVTE10V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Bit Bit Name Initianl Value R/W
1
IRIC
0
R/(W) * I
Description
Indicates that the I
request to the CPU.
IRIC is set at different times depending on the FS bit in
SAR, the FSX bit in SARX, and the WAIT bit in ICMR. See
section 13.4.7, IRIC Setting Timing and SCL Control. The
conditions under which IRIC is set also differ depending on
the setting of the ACKE bit in ICCR.
[Setting conditions]
I
When the AL flag is set to 1 after bus arbitration is lost while
the ALIE bit is 1
I
2
2
2
C Bus Interface Interrupt Request Flag
C bus format master mode:
C bus format slave mode:
When a start condition is detected in the bus line state
after a start condition is issued (when the ICDRE flag is
set to 1 because of first frame transmission)
When a wait is inserted between the data and
acknowledge bit when the WAIT bit is 1 (fall of the 8th
transmit/receive clock)
At the end of data transfer (rise of the 9th
transmit/receive clock while no wait is inserted)
When a slave address is received after bus arbitration is
lost (the first frame after the start condition)
If 1 is received as the acknowledge bit (when the ACKB
bit in ICSR is set to 1) when the ACKE bit is 1
When the slave address (SVA or SVAX) matches (when
the AAS or AASX flag in ICSR is set to 1) and at the
end of data transfer up to the subsequent
retransmission start condition or stop condition
detection (rise of the 9th transmit/receive clock)
When the general call address is detected (when 0 is
received as the R/W bit and the ADZ flag in ICSR is set
to 1) and at the end of data reception up to the
subsequent retransmission start condition or stop
condition detection (rise of the 9th receive clock)
If 1 is received as the acknowledge bit (when the ACKB
bit in ICSR is set to 1) while the ACKE bit is 1
When a stop condition is detected (when the STOP or
ESTP flag in ICSR is set to 1) while the STOPIM bit is 0
Rev. 2.00 Mar 21, 2006 page 283 of 518
2
C bus interface has issued an interrupt
Section 13 I
2
C Bus Interface (IIC)
REJ09B0299-0200
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