DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 381

MCU 3V 64K 100-TQFP

DF2110BVTE10

Manufacturer Part Number
DF2110BVTE10
Description
MCU 3V 64K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2110BVTE10

Core Processor
H8S/2000
Core Size
16-Bit
Speed
10MHz
Connectivity
Host Interface (LPC), I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
82
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Other names
HD64F2110BVTE10
HD64F2110BVTE10

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2110BVTE10V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
14.3
The keyboard buffer controller has the following registers for each channel.
14.3.1
KBCRH indicates the operating status of the keyboard buffer controller.
Bit
7
6
5
4
Keyboard control register H (KBCRH)
Keyboard control register L (KBCRL)
Keyboard data buffer register (KBBR)
Bit Name
KBIOE
KCLKI
KDI
KBFSEL
Register Descriptions
Keyboard Control Register H (KBCRH)
Initial Value
0
1
1
1
R/W
R/W
R
R
R/W
Description
Keyboard In/Out Enable
Selects whether or not the keyboard buffer controller
is used.
0: The keyboard buffer controller is non-operational
(KCLK and KD signal pins have port functions)
1: The keyboard buffer controller is enabled for
transmission and reception (KCLK and KD signal pins
are in the bus drive state)
Keyboard Clock In
Monitors the KCLK I/O pin. This bit cannot be
modified.
0: KCLK I/O pin is low
1: KCLK I/O pin is high
Keyboard Data In:
Monitors the KDI I/O pin. This bit cannot be modified.
0: KD I/O pin is low
1: KD I/O pin is high
Keyboard Buffer Register Full Select
Selects whether the KBF bit is used as the keyboard
buffer register full flag or as the KCLK fall interrupt
flag. When KBFSEL is cleared to 0, the KBE bit in
KBCRL should be cleared to 0 to disable reception.
0: KBF bit is used as KCLK fall interrupt flag
1: KBF bit is used as keyboard buffer register full flag
Rev. 2.00 Mar 21, 2006 page 341 of 518
Section 14 Keyboard Buffer Controller
REJ09B0299-0200

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