DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 401

MCU 3V 64K 100-TQFP

DF2110BVTE10

Manufacturer Part Number
DF2110BVTE10
Description
MCU 3V 64K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2110BVTE10

Core Processor
H8S/2000
Core Size
16-Bit
Speed
10MHz
Connectivity
Host Interface (LPC), I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
82
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Other names
HD64F2110BVTE10
HD64F2110BVTE10

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2110BVTE10V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
15.3.1
HICR0 and HICR1 contain control bits that enable or disable host interface functions, control bits
that determine pin output and the internal state of the host interface, and status flags that monitor
the internal state of the host interface.
Bit
7
6
5
HICR0
Bit Name Initial Value Slave Host Description
LPC3E
LPC2E
LPC1E
Host Interface Control Registers 0 and 1 (HICR0, HICR1)
0
0
0
R/W
R/W
R/W
R/W
LPC Enable 3 to 1
Enable or disable the host interface function in
single-chip mode. When the host interface is enabled
(one of the three bits is set to 1), processing for data
transfer between the slave processor (this LSI) and
the host processor is performed using pins LAD3 to
LAD0, LFRAME, LRESET, LCLK, SERIRQ,
CLKRUN, and LPCPD.
0: LPC channel 3 operation is disabled
No address (LADR3) matches for IDR3, ODR3,
STR3, or TWR0 to TWR15
1: LPC channel 3 operation is enabled
0: LPC channel 2 operation is disabled
No address (H'0062, 66) matches for IDR2, ODR2, or
STR2
1: LPC channel 2 operation is enabled
0: LPC channel 1 operation is disabled
No address (H'0060, 64) matches for IDR1, ODR1, or
STR1
1: LPC channel 1 operation is enabled
LPC3E
LPC2E
LPC1E
Section 15 Host Interface LPC Interface (LPC)
Rev. 2.00 Mar 21, 2006 page 361 of 518
REJ09B0299-0200

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