DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 145
![MCU 3V 64K 100-TQFP](/photos/28/61/286108/100-tqfp_sml.jpg)
DF2110BVTE10
Manufacturer Part Number
DF2110BVTE10
Description
MCU 3V 64K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.DF2110BVTE10V.pdf
(561 pages)
Specifications of DF2110BVTE10
Core Processor
H8S/2000
Core Size
16-Bit
Speed
10MHz
Connectivity
Host Interface (LPC), I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
82
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Other names
HD64F2110BVTE10
HD64F2110BVTE10
HD64F2110BVTE10
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2110BVTE10V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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7.6.2
P5DR stores output data for port 5 pins.
Bit
7
to
3
2
1
0
7.6.3
SPS1 *
ICE
CKE1
C/A
CKE0
P52DDR
Pin Function
Note: * When this pin is used as the SCL0 I/O pin by setting 1 to the SPS1 bit of SPSR, bits CKE1
P52/ExSCK1*/SCL0
The pin function is switched as shown below according to the combination of the CKE1 and
CKE0 bits in SCR, the C/A bit in SMR of SCI_1, the SPS1 bit* in SPSR, the ICE bit in ICCR
of IIC_0, and the P52DDR bit.
and CKE0 in SCR of SCI_1 and bit C/A in SMR must all be cleared to 0. SCL0 is an NMOS
open-drain output.
When set as the P52 output pin or ExSCK1 output pin, this pin is an NMOS push-pull
output.
The program development tool (emulator) does not support this function.
Bit Name
P52DR
P51DR
P50DR
Port 5 Data Register (P5DR)
Pin Functions
input
P52
pin
0
Initial Value
All 1
0
0
0
0
output
P52
pin
0
1
I/O pin
SCL0
1
R/W
R/W
R/W
R/W
input
P52
pin
0
Description
Reserved
The initial value should not be changed.
If a port 5 read is performed while P5DDR bits are
set to 1, the P5DR values are read directly,
regardless of the actual pin states. If a port 5 read
is performed while P5DDR bits are cleared to 0,
the pin states are read.
0
output
P52
pin
1
0
Rev. 2.00 Mar 21, 2006 page 105 of 518
ExSCK1 *
0
output
pin
1
0
1
ExSCK1 *
output
pin
1
Section 7 I/O Ports
REJ09B0299-0200
ExSCK1 *
input
pin
1
I/O pin
SCL0
1
0
0
0
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