DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 26

• Manufacturer Part Number: DF2110BVTE10
• Description: MCU 3V 64K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2110BVTE10

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: Host Interface (LPC), I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: HD64F2110BVTE10; HD64F2110BVTE10

14.5 Usage Notes ...................................................................................................................... 356
Section 15 Host Interface LPC Interface (LPC)
15.1 Features ............................................................................................................................. 357
15.2 Input/Output Pins .............................................................................................................. 359
15.3 Register Descriptions ........................................................................................................ 360
15.4 Operation .......................................................................................................................... 390
15.5 Interrupt Sources............................................................................................................... 403
15.6 Usage Notes ...................................................................................................................... 405
Section 16 RAM
Section 17 ROM
17.1 Features ............................................................................................................................. 409
17.2 Mode Transitions .............................................................................................................. 411
17.3 Block Configuration.......................................................................................................... 414
Rev. 2.00 Mar 21, 2006 page xxiv of xxxviii
14.4.6 KBF Setting Timing and KCLK Control ............................................................. 353
14.4.7 Receive Timing.................................................................................................... 354
14.4.8 KCLK Fall Interrupt Operation............................................................................ 355
14.5.1 KBIOE Setting and KCLK Falling Edge Detection............................................. 356
14.5.2 Module Stop Mode Setting .................................................................................. 356
15.3.1 Host Interface Control Registers 0 and 1 (HICR0, HICR1)................................. 361
15.3.2 Host Interface Control Registers 2 and 3 (HICR2, HICR3)................................. 368
15.3.3 LPC Channel 3 Address Register (LADR3) ........................................................ 371
15.3.4 Input Data Registers 1 to 3 (IDR1 to IDR3) ........................................................ 372
15.3.5 Output Data Registers 1 to 3 (ODR1 to ODR3)................................................... 373
15.3.6 Bidirectional Data Registers 0 to 15 (TWR0 to TWR15) .................................... 373
15.3.7 Status Registers 1 to 3 (STR1 to STR3)............................................................... 374
15.3.8 SERIRQ Control Registers 0 and 1 (SIRQCR0, SIRQCR1) ............................... 381
15.3.9 Host Interface Select Register (HISEL) ............................................................... 389
15.4.1 Host Interface Activation ..................................................................................... 390
15.4.2 LPC I/O Cycles .................................................................................................... 391
15.4.3 A20 Gate .............................................................................................................. 393
15.4.4 Host Interface Shutdown Function (LPCPD)....................................................... 396
15.4.5 Host Interface Serialized Interrupt Operation (SERIRQ) .................................... 400
15.4.6 Host Interface Clock Start Request (CLKRUN) .................................................. 402
15.5.1 IBFI1, IBFI2, IBFI3, and ERRI ........................................................................... 403
15.5.2 SMI, HIRQ1, HIRQ6, HIRQ9, HIRQ10, HIRQ11, and HIRQ12........................ 403
15.6.1 Module Stop Mode Setting .................................................................................. 405
15.6.2 Notes on Using Host Interface ............................................................................. 405
.................................................................................................................. 407
.................................................................................................................. 409
......................................................... 357