D6417760BP200ADV Renesas Electronics America, D6417760BP200ADV Datasheet - Page 941

• Manufacturer Part Number: D6417760BP200ADV
• Description: IC SUPER H MPU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of D6417760BP200ADV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

23.3.3
SPSCR is a 32-bit readable/writable register that enables or disables interrupts or FIFO mode,
selects either LSB first or MSB first in transmitting/receiving date, and master or slave mode.
If any of the FFEN, LMSB, CSA or MASL bit values are changed, then the module will undergo
the HSPI software reset.
Initial value:
Initial value:
Bit
31 to 14 ⎯
13
12
11
10
9
R/W:
R/W:
Bit:
Bit:
System Control Register (SPSCR)
Bit Name
TEIE
THIE
RNIE
RHIE
RFIE
31
15
R
R
-
-
-
-
30
14
R
R
-
-
-
-
TEIE THIE RNIE RHIE
R/W
29
13
R
0
-
-
Initial Value
All ⎯
0
0
0
0
0
R/W
28
12
R
0
-
-
R/W
27
11
R
0
-
-
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
26
10
R
0
-
-
RFIE FFEN
R/W
25
R
9
0
-
-
Description
Reserved
These bits are always read as an undefined
value. The write value should always be 0.
Transmit FIFO Empty Interrupt Enable
0:Transmit FIFO empty interrupt disabled
1:Transmit FIFO empty interrupt enabled
Transmit FIFO Halfway Interrupt Enable
0:Transmit FIFO halfway interrupt disabled
1:Transmit FIFO halfway interrupt enabled
Receive FIFO Not Empty Interrupt Enable
0: Receive FIFO not empty interrupt disabled
1: Receive FIFO not empty interrupt enabled
Receive FIFO Halfway Interrupt Enable
0: Receive FIFO halfway interrupt disabled
1: Receive FIFO halfway interrupt enabled
Receive FIFO Full Interrupt Enable
0: Receive FIFO full interrupt disabled
1: Receive FIFO full interrupt enabled
R/W
24
R
8
0
-
-
LMSB CSV
R/W
23
R
7
0
-
-
Rev. 2.00 Feb. 12, 2010 Page 857 of 1330
R/W
22
R
6
1
-
-
CSA
R/W
21
R
5
0
-
-
TFIE
R/W
20
R
4
0
-
-
ROIE RXDE TXDE MASL
R/W
19
R
3
0
-
-
REJ09B0554-0200
R/W
18
R
2
0
-
-
R/W
17
R
1
0
-
-
R/W
16
R
0
0
-
-