D6417760BP200ADV Renesas Electronics America, D6417760BP200ADV Datasheet - Page 383
D6417760BP200ADV
Manufacturer Part Number
D6417760BP200ADV
Description
IC SUPER H MPU ROMLESS 256BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of D6417760BP200ADV
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D6417760BP200ADV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Access
Size
Byte
Word
Long-
word
Quad-
word
Data Configuration
Table 10.10 32-Bit Off-chip Device/Big-Endian Access and Data Alignment
Operation
Quadword
Longword
Address No.
4n
4n+1
4n+2
4n+3
4n
4n+2
4n
8n
8n+4
Word
Byte
MSB
MSB
MSB
MSB
63 to 56
1
1
1
1
1
1
1
1
2
Data
Data 31 to 24
Data 15 to 8
Data 7 to 0
D31 to
D24
Data
7 to 0
—
—
—
Data
15 to 8
—
Data
31 to 24
Data
63 to 56
Data
31 to 24
55 to 48
Data
LSB
D23 to
D16
—
Data
7 to 0
—
—
Data
7 to 0
—
Data
23 to 16
Data
55 to 48
Data
23 to 16
Data Bus
47 to 40
Data
Data 23 to 16
Data 7 to 0
D15 to D8D7 to D0 WE3,
—
—
Data
7 to 0
—
—
Data
15 to 8
Data
15 to 8
Data
47 to 40
Data
15 to 8
39 to 32
Data
—
—
—
Data
7 to 0
—
Data
7 to 0
Data
7 to 0
Data
39 to 32
Data
7 to 0
LSB
31 to 24
Data
Rev. 2.00 Feb. 12, 2010 Page 299 of 1330
Asserted Asserted
Data 15 to 8
DQM3
Asserted
Asserted Asserted Asserted Asserted
Asserted Asserted Asserted Asserted
Asserted Asserted Asserted Asserted
23 to 16
Data
WE2,
DQM2
Asserted
Strobe Signals
15 to 8
WE1,
DQM1
Asserted
Asserted Asserted
Data
REJ09B0554-0200
Data 7 to 0
WE0,
DQM0
Asserted
7 to 0
Data
LSB
LSB
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