D6417760BP200ADV Renesas Electronics America, D6417760BP200ADV Datasheet - Page 668

• Manufacturer Part Number: D6417760BP200ADV
• Description: IC SUPER H MPU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of D6417760BP200ADV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Rev. 2.00 Feb. 12, 2010 Page 584 of 1330
REJ09B0554-0200
Bit
6
5
Bit Name
RIE
TE
Initial Value
0
0
R/W
R/W
R/W
Description
Receive Interrupt Enable
Enables or disables generation of a receive-data-
full interrupt (RXI) request when the RDF flag or
DR flag in SCFSR is set to 1, a receive-error
interrupt (ERI) request when the ER flag in
SCFSR is set to 1, and a break interrupt (BRI)
request when the BRK flag in SCFSR or the
ORER flag in SCLSR is set to 1.
0: Receive-data-full interrupt (RXI) request,
1: Receive-data-full interrupt (RXI) request,
Note: An RXI interrupt request can be cleared by
Enables or disables the start of serial
transmission by the SCIF.
Serial transmission is started when transmit data
is written to SCFTDR while the TE bit is set to 1.
0: Transmission disabled
1: Transmission enabled*
Note: SCSMR and SCFCR settings must be
Transmit Enable
receive-error interrupt (ERI) request, and
break interrupt (BRI) request disabled
receive-error interrupt (ERI) request, and
break interrupt (BRI) request enabled
reading 1 from the RDF or DR flag, then
clearing the flag to 0, or by clearing the RIE
bit to 0. ERI and BRI interrupt requests can
be cleared by reading 1 from the ER, BRK,
or ORER flag, then clearing the flag to 0, or
by clearing the RIE and REIE bits to 0.
made, the transmission format decided,
and the transmit FIFO reset, before the TE
bit is set to 1.