D6417760BP200ADV Renesas Electronics America, D6417760BP200ADV Datasheet - Page 803

IC SUPER H MPU ROMLESS 256BGA

D6417760BP200ADV

Manufacturer Part Number
D6417760BP200ADV
Description
IC SUPER H MPU ROMLESS 256BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of D6417760BP200ADV

Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
D6417760BP200ADV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Bit
24
23 to 4
3
2
Bit Name
DIRQ
CHNO1
CHNO0
Initial Value
0
0
0
R/W
R
R
R
R
Description
Data Interrupt Status Flag
This status flag indicates that the SSI module
requires that data be either read out or written in.
This bit is set to 1 regardless of the setting of
DIEN bit, so that polling will be possible.
The interrupt can be masked by clearing DIEN bit
to 0, but writing 0 in this bit will not clear the
interrupt.
If DIRQ = 1 and DIEN = 1, then an interrupt will be
generated.
When TRMD = 0 (Receive Mode):
0: No unread data exists in SSIRDR.
1: Unread data exists in SSIRDR.
When TRMD = 1 (Transmit Mode):
0: The transmit buffer is full.
1: The transmit buffer is empty, and requires that
Reserved
These bits are always read as an undefined value.
The write value should always be 0.
Channel Number
The number indicates the current channel.
When TRMD = 0 (Receive Mode):
This bit indicates to which channel the current
data in SSIRDR belongs. When the data in
SSIRDR is updated by transfer from the shift
register, this value will change.
When TRMD = 1 (Transmit Mode):
This bit indicates the data of which channel should
be written in SSITDR. When data is copied to the
shift register, regardless whether the data is
written in SSITDR, this value will change.
data be written in SSITDR.
Rev. 2.00 Feb. 12, 2010 Page 719 of 1330
REJ09B0554-0200

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