D6417760BP200ADV Renesas Electronics America, D6417760BP200ADV Datasheet - Page 274
D6417760BP200ADV
Manufacturer Part Number
D6417760BP200ADV
Description
IC SUPER H MPU ROMLESS 256BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of D6417760BP200ADV
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D6417760BP200ADV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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8.3.2
A priority ranking is provided for all exceptions for use in determining which of two or more
simultaneously generated exceptions should be accepted. Five of the general exceptions—general
illegal instruction exception, slot illegal instruction exception, general FPU disable exception, slot
FPU disable exception, and unconditional trap exception—are detected in the process of
instruction decoding, and do not occur simultaneously in the instruction pipeline. These
exceptions therefore all have the same priority. General exceptions are detected in the order of
instruction execution. However, exception handling is performed in the order of instruction flow
(program order). Thus, an exception for an earlier instruction is accepted before that for a later
instruction. An example of the order of acceptance for general exceptions is shown in figure 8.2.
Rev. 2.00 Feb. 12, 2010 Page 190 of 1330
REJ09B0554-0200
Exception Source Acceptance
Figure 8.2 Example of General Exception Acceptance Order
Pipeline flow:
Order of detection:
Order of exception handling:
Instruction n
Instruction n + 1
Instruction n + 2
Instruction n + 3
General illegal instruction exception (instruction n + 1) and
TLB miss (instruction n + 2) are detected simultaneously
TLB miss (instruction n)
TLB miss (instruction n)
Re-execution of instruction n
General illegal instruction exception
(instruction n + 1)
Re-execution of instruction n + 1
TLB miss (instruction n + 2)
Re-execution of instruction n + 2
Execution of instruction n + 3
Legend:
IF
ID : Instruction decode
EX : Instruction execution
MA : Memory access
WB : Write-back
: Instruction fetch
IF
IF
ID
ID
IF
TLB miss (instruction access)
General illegal instruction exception
EX
EX
ID
IF
MA
MA
EX MA WB
ID
TLB miss (data access)
Program order
WB
WB
EX MA WB
1
2
3
4
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