D6417760BP200ADV Renesas Electronics America, D6417760BP200ADV Datasheet - Page 1048

• Manufacturer Part Number: D6417760BP200ADV
• Description: IC SUPER H MPU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of D6417760BP200ADV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

26.3.15 Data Register (DR)
DR is a register for reading/writing FIFO data.
Word/byte access is enabled to addresses of this register.
Initial value:
The following shows examples of DR access.
When data is written to DR in the following steps 1 to 4, the transmit data is stored in the FIFO as
shown in figure 26.2.
1. Write word data H'0123 to DR.
2. Write byte data H'45 to DR.
3. Write word data H'6789 to DR.
4. Write byte data H'AB to DR.
When the receive data is stored in the FIFO as shown in figure 26.2 (for example, after data is
started to be received while the FIFO is empty and data is received in the order of H'01, H'23, ...,
H'AB), data can be read from DR in the following steps 5 to 8.
5. Read byte data H'01 from DR.
6. Read word data H'2345 from DR.
7. Read byte data H'67 from DR.
8. Ready word data H'89AB from DR.
Rev. 2.00 Feb. 12, 2010 Page 964 of 1330
REJ09B0554-0200
Bit
15 to 0
R/W:
Bit:
R/W
Bit
Name
DR
15
-
R/W
14
-
Initial
Value
—
R/W
13
-
R/W
12
-
R/W
11
-
R/W
R/W
R/W
10
-
Description
Register for reading/writing FIFO data.
Word/byte access is enabled.
When DR is accessed in words, the upper and lower
bytes are transmitted or received in that order. Word
access and byte access can be done in random order.
However, (DR address + 1) cannot be accessed in
bytes.
R/W
9
-
R/W
8
-
DR
R/W
7
-
R/W
6
-
R/W
5
-
R/W
4
-
R/W
3
-
R/W
2
-
R/W
1
-
R/W
0
-