D6417760BP200ADV Renesas Electronics America, D6417760BP200ADV Datasheet - Page 229
D6417760BP200ADV
Manufacturer Part Number
D6417760BP200ADV
Description
IC SUPER H MPU ROMLESS 256BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of D6417760BP200ADV
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D6417760BP200ADV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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6.6.3
ITLB data array 2 is allocated to addresses H'F380 0000 to H'F3FF FFFF in the P4 area. A data
array access requires a 32-bit address field specification (when reading or writing) and a 32-bit
data field specification (when writing). Information for selecting the entry to be accessed is
specified in the address field, and SA and TC to be written to data array 2 are specified in the data
field.
In the address field, bits [31:23] have the value H'F38 indicating ITLB data array 2 and the entry is
specified by bits [9:8].
In the data field, bit [3] indicates TC and bits [2:0] indicate SA.
The following two kinds of operation can be used on ITLB data array 2:
1. ITLB data array 2 read
2. ITLB data array 2 write
SA and TC are read into the data field from the ITLB entry corresponding to the entry set in
the data field.
SA and TC specified in the data field are written to the ITLB entry corresponding to the entry
set in the address field.
ITLB Data Array 2
Address field
Data field
SZ[1:0]:
Figure 6.13 Memory-Mapped ITLB Data Array 1
31
31
1 1 1 1 0 0
PPN:
30 29 28
V:
E:
Physical page number
Validity bit
Entry
Page size bits
1 1
24
23
0
PPN
PR:
SH:
C:
:
Protection key data
Cacheability bit
Share status bit
Reserved bits (write value should be 0,
and read value is undefined )
Rev. 2.00 Feb. 12, 2010 Page 145 of 1330
10 9 8 7
10 9 8 7
E
V
SZ1
PR
6 5
SZ0
4 3
C
2 1 0
REJ09B0554-0200
SH
0
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