D6417760BP200ADV Renesas Electronics America, D6417760BP200ADV Datasheet - Page 802
D6417760BP200ADV
Manufacturer Part Number
D6417760BP200ADV
Description
IC SUPER H MPU ROMLESS 256BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of D6417760BP200ADV
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D6417760BP200ADV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Rev. 2.00 Feb. 12, 2010 Page 718 of 1330
REJ09B0554-0200
Bit
26
25
Bit Name
OIRQ
IIRQ
Initial Value
0
1
R/W
R/W*
R
Description
Overflow Error Interrupt Status Flag
This status flag indicates that the data has been
supplied at a higher rate than the required rate.
This bit is set to 1 regardless of the setting of
OIEN bit. In order to clear it to 0, write 0 in it.
If OIRQ = 1 and OIEN = 1, then an interrupt will
be generated.
When TRMD = 0 (Receive Mode):
If OIRQ = 1, it indicates that the previous unread
data had not been read out before new unread
data was written in SSIRDR. This may cause the
loss of data, which can lead to destruction of
multi-channel data.
Note:
When TRMD = 1 (Transmit Mode):
If OIRQ = 1, it indicates that SSITDR had data
written in before the data in SSITDR was
transferred to the shift register. This may cause
the loss of data, which can lead to destruction of
multi-channel data.
Idle Mode Interrupt Status Flag
This status flag indicates whether the SSI module
is in the idle status. This bit is set to 1 regardless
of the setting of IIEN bit, so that polling will be
possible.
The interrupt can be masked by clearing IIEN bit
to 0, but writing 0 in this bit will not clear the
interrupt.
If IIRQ = 1 and IIEN = 1, then an interrupt will be
generated.
0: The SSI module is not in the idle status.
1: The SSI module is in the idle status.
the data buffer will be overwritten by the
next data sent from the SSI interface.
When overflow error occurs, the data in
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