D6417760BP200ADV Renesas Electronics America, D6417760BP200ADV Datasheet - Page 652

• Manufacturer Part Number: D6417760BP200ADV
• Description: IC SUPER H MPU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of D6417760BP200ADV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

• Full-duplex communication capability
• On-chip baud rate generator allows any bit rate to be selected.
• Choice of serial clock source: internal clock from baud rate generator or external clock from
• Four interrupt sources
• The DMA controller (DMAC) can be activated to execute a data transfer by issuing a DMA
• When not in use, the SCIF can be stopped by halting its clock supply to reduce power
• In asynchronous mode, modem control functions (SCIF_RTS and SCIF_CTS) are
• The amount of data in the transmit/receive FIFO registers, and the number of receive errors in
• In asynchronous mode, a timeout error (DR) can be detected during reception.
Figure 17.1 shows a block diagram of the SCIF. Figures 17.2 to 17.6 show block diagrams of the
I/O ports in SCIF. There are three channels in this LSI. In figures 17.1 to 17.6, the channels are
omitted and explained. Note that the SCIF_CTS and SCIF_RTS pins are available only in
channels 1 and 2 and not in channel 0.
Rev. 2.00 Feb. 12, 2010 Page 568 of 1330
REJ09B0554-0200
The transmitter and receiver are independent units, enabling transmission and reception to be
performed simultaneously.
The transmitter and receiver both have a 128-stage FIFO buffer structure, enabling continuous
serial data transmission and reception.
SCIF_CLK pin
There are four interrupt sources—transmit-FIFO-data-empty, break, receive-FIFO-data-full,
and receive-error—that can issue requests independently.
transfer request in the event of a transmit-FIFO-data-empty or receive-FIFO-data-full interrupt.
consumption.
provided.(only in channels 1 and 2)
the receive data in the receive FIFO register, can be ascertained.