D6417760BP200ADV Renesas Electronics America, D6417760BP200ADV Datasheet - Page 1075
D6417760BP200ADV
Manufacturer Part Number
D6417760BP200ADV
Description
IC SUPER H MPU ROMLESS 256BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of D6417760BP200ADV
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D6417760BP200ADV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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26.6
26.6.1
In order to transfer data in FIFO with the DMAC, set MMCIF (DMACR) after setting the
DMAC*. Transmit the read command after setting DMACR.
Figure 26.22 shows the operational flow for a read sequence.
• Clear FIFO and make settings in DMACR.
• Read command transmission is started.
• Read data is received from the card.
• After the read sequence, data remains in FIFO. If necessary, write 100 to SET[2:0] in DMACR
• Confirm that the DMAC transfer is completed and set the DMAEN bit in DMACR to 0.
• When the DMAEN bit in DMACR is set to 1, the FIFO_FULL bit in CSTR and FFI bit in
Note: * Access from the DMAC to FIFO must be done in bytes or words.
26.6.2
To transfer data to FIFO with the DMAC, set MMCIF (DMACR) after setting the DMAC. Then,
start transfer to the card after a FIFO ready interrupt. Figure 26.23 shows the operational flow for
write sequence.
• Make settings in DMACR, and set write data to FIFO.
• After receiving write command response, confirm whether data above the condition of
• Confirm that the DMAC transfer is all completed and be sure to set the DMAEN bit in
• When the DMAEN bit in DMACR is set to 1, the FIFO_EMPTY bit in CSTR and the FEI bit
• Some combinations of DMACR settings and data transfer count will generate no FIFO ready
to read all data from FIFO.
INTSTR0 can not be set.
DMACR setting is written to FIFO by a FIFO ready interrupt (FRDYI). Then, set 1 to the
DATAEN bit in OPCR to start write-data transmission.
In a write to the card by stream transfer, the MMCIF continues data transfer to the card even
after a FIFO empty interrupt is detected. Therefore, complete the write sequence after at least
24 card clock cycles.
DMACR to 0.
in INSTR0 can not be set.
interrupt (FRDYI) and data will remain in FIFO. In this case, set the DATAEN bit in OPCR to
1 to start write-data transmission.
Operations when Using DMA
Operation in Read Sequence
Operation in Write Sequence
Rev. 2.00 Feb. 12, 2010 Page 991 of 1330
REJ09B0554-0200
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