D6417760BP200ADV Renesas Electronics America, D6417760BP200ADV Datasheet - Page 589

• Manufacturer Part Number: D6417760BP200ADV
• Description: IC SUPER H MPU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of D6417760BP200ADV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

13.2.1
WTCNT is an 8-bit readable/writable counter that counts up on the selected clock. When WTCNT
overflows, a reset is generated in watchdog timer mode, or an interrupt is generated in interval
timer mode. WTCNT is initialized to H'00 only by a power-on reset via the RESET pin.
To write to WTCNT, use a word-size access with the upper byte set to H'5A. To read from
WTCNT, use a byte-size access.
13.2.2
WTCSR is an 8-bit readable/writable register containing bits for selecting the clock used for
counting and timer mode, and overflow flags.
To write to WTCSR, use a word-size access with the upper byte set to H'A5. To read from
WTCSR, use a byte-size access.
Bit
7
6
TME
WT/IT
Watchdog Timer Counter (WTCNT)
Watchdog Timer Control/Status Register (WTCSR)
Bit Name
Initial value:
Initial value:
Initial Value
0
0
R/W:
R/W:
Bit:
Bit:
TME
R/W
R/W
7
0
7
0
WT/IT
R/W
R/W
6
0
6
0
R/W Description
R/W Timer Enable
R/W Timer Mode Select
RSTS WOVF IOVF CKS2 CKS1 CKS0
R/W
R/W
5
0
5
0
Specifies starting and stopping of timer operation.
Clear this bit to 0 when using the WDT in standby
mode or to change a clock frequency.
0: Up-count stopped, WTCNT value retained
1: Up-count started
Specifies whether the WDT is used as a watchdog
timer or interval timer. Up counting may not be
performed correctly if this bit is modified while the
WDT is running.
0: Interval timer mode
1: Watchdog timer mode
R/W
R/W
4
0
4
0
R/W
R/W
3
0
3
0
Rev. 2.00 Feb. 12, 2010 Page 505 of 1330
R/W
R/W
2
0
2
0
R/W
R/W
1
0
1
0
R/W
R/W
0
0
0
0
REJ09B0554-0200