D6417760BP200ADV Renesas Electronics America, D6417760BP200ADV Datasheet - Page 197

• Manufacturer Part Number: D6417760BP200ADV
• Description: IC SUPER H MPU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of D6417760BP200ADV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 6 Memory Management Unit (MMU)
Section 6 Memory Management Unit (MMU)
The SH-4 supports an 8-bit address space identifier, a 32-bit virtual address space, and a 29-bit
external memory space. Address translation from virtual addresses to physical addresses is
enabled by the memory management unit (MMU) in the SH-4. The MMU performs high-speed
address translation by caching user-created address translation table information in an address
translation buffer (translation lookaside buffer: TLB).
The SH-4 has four instruction TLB (ITLB) entries and 64 unified TLB (UTLB) entries. UTLB
copies are stored in the ITLB by hardware. A paging system is used for address translation, with
four page sizes (1, 4, and 64 Kbytes, and 1 Mbyte) supported. It is possible to set the virtual
address space access right and implement memory protection independently for privileged mode
and user mode.
6.1
Overview of the MMU
The MMU was conceived as a means of making efficient use of physical memory. As shown in
figure 6.1, when a process is smaller in size than the physical memory, the entire process can be
mapped onto physical memory, but if the process increases in size to the point where it does not fit
into physical memory, it becomes necessary to divide the process into smaller parts, and map the
parts requiring execution onto physical memory as occasion arises ((1) in figure 6.1). Having this
mapping onto physical memory executed consciously by the process itself imposes a heavy burden
on the process. The virtual memory system was devised as a means of handling all physical
memory mapping to reduce this burden ((2) in figure 6.1). With a virtual memory system, the size
of the available virtual memory is much larger than the actual physical memory, and processes are
mapped onto this virtual memory. Thus processes only have to consider their operation in virtual
memory, and mapping from virtual memory to physical memory is handled by the MMU. The
MMU is normally managed by the OS, and physical memory switching is carried out so as to
enable the virtual memory required by a process to be mapped smoothly onto physical memory.
Physical memory switching is performed via secondary storage, etc.
The virtual memory system that came into being in this way works to best effect in a time sharing
system (TSS) that allows a number of processes to run simultaneously ((3) in figure 6.1). Running
a number of processes in a TSS did not increase efficiency since each process had to take account
of physical memory mapping. Efficiency is improved and the load on each process reduced by the
use of a virtual memory system ((4) in figure 6.1). In this virtual memory system, virtual memory
is allocated to each process. The task of the MMU is to map a number of virtual memory areas
onto physical memory in an efficient manner. It is also provided with memory protection functions
to prevent a process from inadvertently accessing another process’s physical memory.
Rev. 2.00 Feb. 12, 2010 Page 113 of 1330
REJ09B0554-0200