D6417760BP200ADV Renesas Electronics America, D6417760BP200ADV Datasheet - Page 718
D6417760BP200ADV
Manufacturer Part Number
D6417760BP200ADV
Description
IC SUPER H MPU ROMLESS 256BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of D6417760BP200ADV
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D6417760BP200ADV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Rev. 2.00 Feb. 12, 2010 Page 634 of 1330
REJ09B0554-0200
Bit
4
3
2
1
0
Bit
Name
RE
WAIT_IE
TEIE
CKE1
CKE0
Initial
Value
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Description
Receive Enable
Enables/disables serial reception.
0: Disables reception*
1: Enables reception*
Notes: 1.
Wait Enable
Enables or disables wait error interrupt requests.
0: Disables wait error interrupt (SIMERI) requests
1: Enables wait error interrupt (SIMERI) requests
Enables or disables transmission end interrupt (SIMTEI)
requests when transmission ends and the TEND flag is set to
1.
0: Disables transmission end interrupt (SIMTEI) requests*
1: Enables transmission end interrupt (SIMTEI) requests*
Note: * After the 1 in the TDRE flag in SISSR is read, SIMTEI
Clock Enable 1, 0
Select the clock source for the smart card interface, and
enables or disables clock output from the SIM_CLK pin.
00: Output pin fixed at low level output
01: Output pin set for clock output
10: Output pin fixed at high level output
11: Output pin set for clock output
Transmit end interrupt enable
can be cancelled either by writing transmit data to
SITDR and then clearing the TEND bit, or by clearing
the TEIE bit to 0.
2.
Note that clearing the RE bit to 0 has no effect
on the RDRF, PER, ERS, ORER, or WAIT_ER
flags. The state of these flags will be
maintained.
If the start bit is detected in this state, serial
reception is initiated. Before setting the RE bit to
1, SISMR and SISCMR registers must always be
set, to determine the reception format.
2
1
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