D6417760BP200ADV Renesas Electronics America, D6417760BP200ADV Datasheet - Page 1047

IC SUPER H MPU ROMLESS 256BGA

D6417760BP200ADV

Manufacturer Part Number
D6417760BP200ADV
Description
IC SUPER H MPU ROMLESS 256BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of D6417760BP200ADV

Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
D6417760BP200ADV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
26.3.14 Transfer Clock Control Register (CLKON)
CLKON controls the transfer clock frequency and clock ON/OFF.
Bits CSEL2 to CSEL0 must be set to 100 for the peripheral clock to be 20-MHz in order to
achieve a 20-Mbps transfer clock in the MMCIF. At this time, bits CSEL2 to CSEL0 should be set
to 000 for the 200-kbps transfer clock in Card Identification Mode in MMC mode.
In a command sequence, do not perform clock ON/OFF or frequency modification.
Bit
7
6 to 3
2
1
0
Bit
Name
CLKON
CSEL2
CSEL1
CSEL0
Initial
Value
0
All 0
0
0
0
Initial value:
R/W:
Bit:
R/W
R/W
R
R/W
R/W
R/W
CLKON
R/W
7
0
Clock On
Description
0: Fixes the transfer clock output from the MCCLK pin to
1: Outputs the transfer clock from the MCCLK pin.
Reserved
These bits are always read as 0. The write value should
always be 0.
Transfer Clock Frequency Select
000: Uses the 1/100-divided peripheral clock as a transfer
001: Uses the 1/8-divided peripheral clock as a transfer
010: Uses the 1/4-divided peripheral clock as a transfer
011: Uses the 1/2-divided peripheral clock as a transfer
100: Use the peripheral clock as a transfer clock.
101 to 111: Setting prohibited
R
6
-
0
low level.
clock.
clock.
clock.
clock.
R
5
0
-
4
-
0
R
R
3
0
-
Rev. 2.00 Feb. 12, 2010 Page 963 of 1330
CSEL2 CSEL1 CSEL0
R/W
2
0
R/W
0
1
R/W
0
0
REJ09B0554-0200

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