D6417760BP200ADV Renesas Electronics America, D6417760BP200ADV Datasheet - Page 1176
D6417760BP200ADV
Manufacturer Part Number
D6417760BP200ADV
Description
IC SUPER H MPU ROMLESS 256BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of D6417760BP200ADV
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D6417760BP200ADV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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30.4
30.4.1
This LCDC is capable of controlling displays with up to 1024 × 1024 dots and 16 bpp (bits per
pixel). The image data for display is stored in system memory, which is shared with the CPU.
This LCDC should read the data from system memory before display.
This LSI has a maximum 32-byte burst memory read operation and a 2.4-kbyte line buffer, so
display failure is unlikely. However, there may be some display problems with certain
configurations. A recommended size at the frame rate of 60 Hz is 320 × 240 dots in 16 bpp or 640
× 480 dots in 8-bpp.
Figure 30.2 shows the valid display and the retrace period.
Rev. 2.00 Feb. 12, 2010 Page 1092 of 1330
REJ09B0554-0200
Operation
Size of LCD Modules Which Can Be Displayed with this LCDC
Hsync Signal
Active Video =Top/Left Border + Addressable Video + Bottom/Right Border
Total H Blank = Hsync Time + Back Porch + Front Porch
Total V Blank = Vsync Time + Back Porch + Front Porch
HTCN = H Total Time
HDCN = H Addressable Video
HSYNP = H Addressable Video + Right Border + Front Porch
HSYNW = Hsync Time
VTLN = V Total Time
CDLN = V Addressable Video
VSYNP = V Addressable Video + Bottom Border + Front porch
VSYNW = Vsync Time
Figure 30.2 Valid Display and the Retrace Period
H AddressableVideo
H total Time
Back Porch
Top Border
V Addressable
Video
Bottom Border
Vsync Time
Front Porch
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