D6417760BP200ADV Renesas Electronics America, D6417760BP200ADV Datasheet - Page 1078
D6417760BP200ADV
Manufacturer Part Number
D6417760BP200ADV
Description
IC SUPER H MPU ROMLESS 256BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of D6417760BP200ADV
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
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Part Number:
D6417760BP200ADV
Manufacturer:
Renesas Electronics America
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26.7
When the little endian is specified, the access size for registers or that for memory where the
corresponding data is stored should be fixed. For example, if data read from the MMCIF with the
word size is written to memory and then it is read from memory with the byte size, data mis-
alignment occurs.
26.8
26.8.1
(1) Summary
The MMCIF may not receive the command response correctly, when it finishes receiving the end
bit of the first data block before receiving the end bit of the command response. It may occur after
MMCIF issued CMD18 to the receive device.
(2) Conditions under which the phenomenon occurs
This phenomenon occurs when all of the following operations occur.
1. The multiblock read command (CMD18) is issued.
2. The transfer data block size is setting to 1, 2, 4, or 8 byte(s).
3. The end bit of the command response is received after the end bit of the data block is received.
(3) Workaround
1. The transfer data block size in Transfer Byte Number Count Register (TBCR) must be more
2. Confirm that the end bit of the command response is received before the end bit of the first
Rev. 2.00 Feb. 12, 2010 Page 994 of 1330
REJ09B0554-0200
than 16 bytes when CMD18 is issued.
data block is received, if the transfer data block size is 1, 2, 4, or 8 bytes when CMD18 is
transmitted.
Keep the below formula in order to confirm that the end bit of the command response is
received before the end bit of the first data block is received.
Please confirm the N
(N
Register Accesses with Little Endian Specification
Usage Note
Notice about The MMCIF transfer data block size in multiblock read command
AC
cycles + Read Data cycles) > (N
AC
and N
CR
in the spec of target devices to communicate.
CR
Cycles + Response cycles)
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