D6417760BP200ADV Renesas Electronics America, D6417760BP200ADV Datasheet - Page 290

• Manufacturer Part Number: D6417760BP200ADV
• Description: IC SUPER H MPU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of D6417760BP200ADV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

(7) Instruction Address Error
• Sources:
• Transition address: VBR + H'0000 0100
• Transition operations:
Rev. 2.00 Feb. 12, 2010 Page 206 of 1330
REJ09B0554-0200
Instruction_address_error()
{
}
⎯ Instruction fetch from other than a word boundary (2n +1)
⎯ Instruction fetch from area H'8000 0000–H'FFFF FFFF in user mode
The virtual address (32 bits) at which this exception occurred is set in TEA, and the
corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates
the ASID when this exception occurred.
The PC and SR contents for the instruction at which this exception occurred are saved in the
SPC and SSR. The R15 contents at this time are saved in SGR.
Exception code H'0E0 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a
branch is made to PC = VBR + H'0100. For details, see section 6, Memory Management Unit
(MMU).
TEA = EXCEPTION_ADDRESS;
PTEH.VPN = PAGE_NUMBER;
SPC = PC;
SSR = SR;
SGR = R15;
EXPEVT = H'0000 00E0;
SR.MD = 1;
SR.RB = 1;
SR.BL = 1;
PC = VBR + H'0000 0100;