D6417760BP200ADV Renesas Electronics America, D6417760BP200ADV Datasheet - Page 370

• Manufacturer Part Number: D6417760BP200ADV
• Description: IC SUPER H MPU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of D6417760BP200ADV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Rev. 2.00 Feb. 12, 2010 Page 286 of 1330
REJ09B0554-0200
Bit
21
20
19
18
17
16
Bit
Name
TPC2
TPC1
TPC0
⎯
RCD1
RCD0
Initial
Value
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R
R/W
R/W
Description
RAS Precharge Period
When synchronous DRAM interface is in use, these bits
specify the minimum number of cycles until the next
bank active command is issued after precharging.
000:
001:
010:
011:
100:
101:
110:
111:
Reserved
This bit is always read as 0. The write value should
always be 0.
RAS-CAS Delay
When using the synchronous DRAM interface, specify
ACTIVE to READ or WRITE delay in these bits.
00: Setting prohibited
01: 2 cycles
10: 3 cycles
11: 4 cycles*
RAS Precharge Time (SDRAM)
1*
2
3
4*
5*
6*
7*
8*
1
1
1
1
1
1
1