D6417760BP200ADV Renesas Electronics America, D6417760BP200ADV Datasheet - Page 900

IC SUPER H MPU ROMLESS 256BGA

D6417760BP200ADV

Manufacturer Part Number
D6417760BP200ADV
Description
IC SUPER H MPU ROMLESS 256BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of D6417760BP200ADV

Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
D6417760BP200ADV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
• Bit Timing Settings
SYNC_SEG: Segment for establishing synchronization of nodes on the CAN bus. (Normal bit
PRSEG:
PHSEG1:
PHSEG2:
The HCAN2 Bit Rate calculation is:
where BRP, TSEG1 and TSEG2 are derived values from the descriptions of the tables above, but
not the actual programmed values. The "+ 1" is for the SYNC_SEG and fixed to 1 time quantum.
BCR Setting Constraints
These constraints allow the setting range shown in the table below for TSET1 and TSEG2 in the
Bit Configuration Register.
Table 22.5 shows the settings of TSEG1 and TSEG2 in CANBCR1. That allow the above-
described settings.
Rev. 2.00 Feb. 12, 2010 Page 816 of 1330
REJ09B0554-0200
Bit rate =
f
TSEG1 > TSEG2 ≥ SJW (SJW = 1 to 4)
TSEG1 + TSEG2 + 1 = 8 to 25 time quanta
CLK
= Pck (peripheral clock (Pck/2 or Pck/3))
edge transitions occur in this segment.)
Segment for compensating for physical delay between networks
Buffer segment for phase drift (positive) (This segment is extended when
synchronization (resynchronization) is established.)
Buffer segment for phase drift (negative) (This segment is shortened when
synchronization (resynchronization) is established.)
SYNC_SEG
BRP × (TSEG1 + TSEG2 + 1)
1
f
1-bit time (8 to 25 quanta)
PRSEG
clk
TSEG1
4-16
PHSEG1
PHSEG2
TSEG2
2-8
Quantum

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