D6417760BP200ADV Renesas Electronics America, D6417760BP200ADV Datasheet - Page 851
D6417760BP200ADV
Manufacturer Part Number
D6417760BP200ADV
Description
IC SUPER H MPU ROMLESS 256BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of D6417760BP200ADV
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
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Quantity
Price
Company:
Part Number:
D6417760BP200ADV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Bit
31 to 14
13 to 0
21.3.18 Low Speed Threshold Register (HcLSThreshold)
HcLSThreshold stores an 11-bit LST value that is used by HC to determine whether or not to
authorize the transfer of the LS packet of up to 8 bytes, before EOF. HC and HCD cannot change
this value.
Initial value:
Initial value:
Bit
31 to 12
11 to 0
R/W:
R/W:
Bit:
Bit:
Bit Name
⎯
PS
Bit Name
⎯
LST
31
15
R
R
0
0
-
-
30
14
-
R
-
R
0
0
29
13
R
R
0
0
-
-
Initial Value
All 0
All 0
Initial Value
All 0
H'628
28
12
R
R
0
0
-
-
R/W
27
11
R
0
0
-
R/W
R/W
R
R/W
R/W
R
R/W
26
10
R
0
1
-
R/W
25
R
-
0
9
1
Description
Reserved
These bits are always read as 0. Always write 0 to
this bit.
Periodic Start
After a hardware reset, this bit is cleared. Then, HCD
sets this bit to 1 during the HC initialization. The
value is calculated roughly as 10% subtracted from
the HcFmInterval value. When HcFmRemaining
reaches the specified value, processing of the
periodic lists will have priority over Control/Bulk
processing. HC will therefore start processing the
Interrupt list after completing the current Control or
Bulk transaction that is in progress.
Description
Reserved
These bits are always read as 0. Always write 0 to
this bit.
LS Threshold
This field contains a value which is compared to the
FR bit prior to initiating a Low Speed transaction. The
transaction is started only if the value of the FR bit is
equivalent to or larger than that of this bit. HCD
calculates the value of this bit taking transmission
and setup overhead into consideration.
R/W
24
R
0
8
0
-
R/W
23
R
0
0
7
-
LST
Rev. 2.00 Feb. 12, 2010 Page 767 of 1330
R/W
22
R
0
6
0
-
R/W
21
R
0
5
1
-
R/W
20
R
0
4
0
-
R/W
19
R
0
3
1
-
REJ09B0554-0200
R/W
18
R
0
2
0
-
R/W
17
R
0
1
0
-
R/W
16
R
0
0
0
-
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