D6417760BP200ADV Renesas Electronics America, D6417760BP200ADV Datasheet - Page 70

• Manufacturer Part Number: D6417760BP200ADV
• Description: IC SUPER H MPU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of D6417760BP200ADV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 25 Audio Codec Interface (HAC)
Figure 25.1 Block Diagram ....................................................................................................... 910
Figure 25.2 AC97 Frame Slot Structure .................................................................................... 926
Figure 25.3 Initialization Sequence ........................................................................................... 929
Figure 25.4 Sample Flowchart for Off-Chip Codec Register Write .......................................... 930
Figure 25.5 Sample Flowchart for Off-Chip Codec Register Read ........................................... 931
Figure 25.6 Sample Flowchart for Off-Chip Codec Register Read (cont)................................. 932
Figure 25.7 Sample Flowchart for Off-Chip Codec Register Read (cont)................................. 933
Section 26 Multimedia Card Interface (MMCIF)
Figure 26.1 Block Diagram of MMCIF..................................................................................... 936
Figure 26.2 DR Access Example............................................................................................... 965
Figure 26.3 Example of Command Sequence for Commands Not Requiring Command
Figure 26.4 Example of Operational Flow for Commands Not Requiring Command
Figure 26.5 Example of Command Sequence for Commands without Data Transfer
Figure 26.6 Example of Command Sequence for Commands without Data Transfer
Figure 26.7 Example of Operational Flow for Commands without Data Transfer.................... 973
Figure 26.8 Example of Command Sequence for Commands with Read Data
Figure 26.9 Example of Command Sequence for Commands with Read Data
Figure 26.10 Example of Command Sequence for Commands with Read Data
Figure 26.11 Example of Command Sequence for Commands with Read Data
Figure 26.12 Example of Operational Flow for Commands with Read Data
Figure 26.13 Example of Operational Flow for Commands with Read Data
Figure 26.14 Example of Operational Flow for Commands with Read Data
Figure 26.15 Example of Command Sequence for Commands with Write Data
Figure 26.16 Example of Command Sequence for Commands with Write Data
Figure 26.17 Example of Command Sequence for Commands with Write Data
Rev. 2.00 Feb. 12, 2010 Page lxviii of lxxxii
REJ09B0554-0200
Response ................................................................................................................ 969
Response ................................................................................................................ 970
(No Data Busy State).............................................................................................. 971
(with Data Busy State) ........................................................................................... 972
(Block Size ≤ FIFO Size) ....................................................................................... 975
(Block Size > FIFO Size) ....................................................................................... 976
(Multiblock Transfer)............................................................................................. 977
(Stream Transfer) ................................................................................................... 978
(Single Block Transfer).......................................................................................... 979
(Multiblock Transfer)............................................................................................. 980
(Stream Transfer) ................................................................................................... 981
(Block Size ≤ FIFO Size) ....................................................................................... 983
(Block Size > FIFO Size) ....................................................................................... 984
(Multiblock Transfer)............................................................................................. 985