DF61657CN35FTV Renesas Electronics America, DF61657CN35FTV Datasheet - Page 92

• Manufacturer Part Number: DF61657CN35FTV
• Description: IC H8SX/1657 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61657CN35FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 35MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 768KB (768K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: 3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 3 MCU Operating Modes
3.2.2
SYSCR controls MAC saturation operation, selects bus width mode for instruction fetch, sets
external bus mode, enables/disables the on-chip RAM, and selects the DTC address mode.
Rev. 2.00 Jun. 28, 2007 Page 66 of 864
REJ09B0341-0200
Bit
15, 14
13
12
11
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Note: * The initial value depends on the startup mode.
Bit Name

MACS

FETCHMD 0
System Control Register (SYSCR)
R/W
R/W
15


1
7
0
Initial Value R/W
All 1
0
1
R/W
R/W
14


1
6
0
MACS
R/W
R/W
R/W
R/W
R/W
R/W
13

0
5
0
Instruction Fetch Mode Select
Descriptions
Reserved
These bits are always read as 1. The write value should
always be 1.
MAC Saturation Operation Control
Selects either saturation operation or non-saturation
operation for the MAC instruction.
0: MAC instruction is non-saturation operation
1: MAC instruction is saturation operation
Reserved
This bit is always read as 1. The write value should
always be 1.
This LSI can prefetch an instruction in units of 16 bits or
32 bits. Select the bus width for instruction fetch
depending on the used memory for the storage of
programs*
0: 32-bit mode
1: 16-bit mode
R/W
R/W
12


1
4
0
1
.
FETCHMD
R/W
R/W
11

0
3
0
R/W
R/W
10


0
2
0
Undefined*
DTCMD
EXPE
R/W
R/W
9
1
1
RAME
R/W
R/W

8
1
0
1