DF61657CN35FTV Renesas Electronics America, DF61657CN35FTV Datasheet - Page 715
DF61657CN35FTV
Manufacturer Part Number
DF61657CN35FTV
Description
IC H8SX/1657 MCU FLASH 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet
1.DF61656N35FTV.pdf
(894 pages)
Specifications of DF61657CN35FTV
Core Processor
H8SX
Core Size
32-Bit
Speed
35MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
82
Program Memory Size
768KB (768K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
For Use With
3DK1657 - DEV EVAL KIT FOR H8SX/1657
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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4. FKEY is cleared to H'00 for protection.
5. The download result must be confirmed by the value of the DPFR parameter. Check the value
6. The operating frequency of the CPU is set in the FPEFEQ parameter for initialization. The
The return value is set in the DPFR parameter.
After the on-chip program storage area is returned to the user-MAT space, the procedure
The values of general registers other than ER0 and ER1 are held during download.
During download, no interrupts can be accepted. However, since the interrupt requests are
To hold a level-detection interrupt request, the interrupt must continue to be input until the
Allocate a stack area of 128 bytes at the maximum in the on-chip RAM before setting the
If access to the flash memory is requested by the DMAC or DTC during download, the
of the DPFR parameter (one byte of start address of the download destination specified by
FTDAR). If the value of the DPFR parameter is H'00, download has been performed normally.
If the value is not H'00, the source that caused download to fail can be investigated by the
description below.
If the value of the DPFR parameter is the same as that before downloading, the setting of
If the value of the DPFR parameter is different from that before downloading, check the SS
settable operating frequency of the FPEFEQ parameter ranges from 8 to 35 MHz. When the
frequency is set otherwise, an error is returned to the FPFR parameter of the initialization
program and initialization is not performed. For details on setting the frequency, see section
18.7.2 (3), Flash Program/Erase Frequency Parameter (FPEFEQ: General Register ER0 of
CPU).
program is resumed. After that, VBR can be set again.
held, when the procedure program is resumed, the interrupts are requested.
download is completed.
SCO bit to 1.
operation cannot be guaranteed. Make sure that an access request by the DMAC or DTC is
not generated.
the start address of the download destination in FTDAR may be abnormal. In this case,
confirm the setting of the TDER bit in FTDAR.
bit or FK bit in the DPFR parameter to confirm the download program selection and FKEY
setting, respectively.
Section 18 Flash Memory (0.18-µm F-ZTAT Version)
Rev. 2.00 Jun. 28, 2007 Page 689 of 864
REJ09B0341-0200
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