DF61657CN35FTV Renesas Electronics America, DF61657CN35FTV Datasheet - Page 59

• Manufacturer Part Number: DF61657CN35FTV
• Description: IC H8SX/1657 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61657CN35FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 35MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 768KB (768K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: 3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

2.6.2
Figure 2.13 shows the data formats in memory.
The H8SX CPU can access word data and longword data which are stored at any addresses in
memory. When word data begins at an odd address or longword data begins at an address other
than a multiple of 4, a bus cycle is divided into two or more accesses. For example, when
longword data begins at an odd address, the bus cycle is divided into byte, word, and byte
accesses. In this case, these accesses are assumed to be individual bus cycles.
However, instructions to be fetched, word and longword data to be accessed during execution of
the stack manipulation, branch table manipulation, block transfer instructions, and MAC
instruction should be located to even addresses.
When SP (ER7) is used as an address register to access the stack, the operand size should be word
size or longword size.
Memory Data Formats
Data Type
1-bit data
Byte data
Word data
Longword data
Figure 2.13 Memory Data Formats
Address 2M + 1
Address 2N + 1
Address 2N + 2
Address 2N + 3
Address
Address 2M
Address 2N
Address L
Address L
MSB
MSB
MSB
7
7
6
Data Format
Rev. 2.00 Jun. 28, 2007 Page 33 of 864
5
4
3
2
1
REJ09B0341-0200
LSB
LSB
LSB
0
0
Section 2 CPU