DF61657CN35FTV Renesas Electronics America, DF61657CN35FTV Datasheet - Page 249

• Manufacturer Part Number: DF61657CN35FTV
• Description: IC H8SX/1657 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61657CN35FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 35MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 768KB (768K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: 3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.11.3
Figure 6.43 shows the timing for transition to the bus released state.
[1] A low level of the BREQ signal is sampled at the rising edge of the Bφ signal.
[2] The bus control signals are driven high at the end of the external space access cycle. It takes two cycles or
[3] The BACK signal is driven low, releasing bus to the external bus master.
[4] The BREQ signal state sampling is continued in the external bus released state.
[5] A high level of the BREQ signal is sampled.
[6] The external bus released cycles are ended one cycle after the BREQ signal is driven high.
[7] When the external space is accessed by an internal bus master during external bus released while the BREQOE
[8] Normally the BREQO signal goes high at the rising edge of the BACK signal.
Bφ
Address bus
Data bus
CSn
AS
RD
LHWR, LLWR
BREQ
BACK
BREQO
more after the low level of the BREQ signal is sampled.
bit is set to 1, the BREQO signal goes low.
Transition Timing
Figure 6.43 Bus Released State Transition Timing
External space
access cycle
[1]
T
1
T
2
[2]
[3]
[4]
External bus released state
[7]
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Rev. 2.00 Jun. 28, 2007 Page 223 of 864
[5]
Section 6 Bus Controller (BSC)
[8]
[6]
REJ09B0341-0200
CPU cycle