DF61657CN35FTV Renesas Electronics America, DF61657CN35FTV Datasheet - Page 380

IC H8SX/1657 MCU FLASH 120TQFP

DF61657CN35FTV

Manufacturer Part Number
DF61657CN35FTV
Description
IC H8SX/1657 MCU FLASH 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of DF61657CN35FTV

Core Processor
H8SX
Core Size
32-Bit
Speed
35MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
82
Program Memory Size
768KB (768K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
For Use With
3DK1657 - DEV EVAL KIT FOR H8SX/1657
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

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Manufacturer
Quantity
Price
Part Number:
DF61657CN35FTV
Manufacturer:
RENESAS
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Part Number:
DF61657CN35FTV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 9 I/O Ports
9.1.2
DR is an 8-bit readable/writable register that stores the output data of the pins to be used as the
general output port.
The initial value of DR is H'00.
9.1.3
PORT is an 8-bit read-only register that reflects the port pin state. A write to PORT is invalid.
When PORT is read, the DR bits that correspond to the respective DDR bits set to 1 are read and
the status of each pin whose corresponding DDR bit is cleared to 0 is also read regardless of the
ICR value.
The initial value of PORT is undefined and is determined based on the port pin state.
Rev. 2.00 Jun. 28, 2007 Page 354 of 864
REJ09B0341-0200
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Note: The lower six bits are valid and the upper two bits are reserved for port 6 registers.
Note:
The lower four bits are valid and the upper four bits are reserved for port B registers.
The lower six bits are valid and the upper two bits are reserved for port 6 registers.
The lower four bits are valid and the upper four bits are reserved for port B registers.
Data Register (PnDR) (n = 1 to 3, 6, A, B, D to F, H, and I)
Port Register (PORTn) (n = 1 to 3, 5, 6, A, B, D to F, H, and I)
Undefined
Pn7DR
R/W
Pn7
R
7
0
7
Undefined
Pn6DR
R/W
Pn6
R
6
0
6
Undefined
Pn5DR
R/W
Pn5
R
5
0
5
Undefined
Pn4DR
R/W
Pn4
R
4
0
4
Undefined
Pn3DR
R/W
Pn3
R
3
0
3
Undefined
Pn2DR
R/W
Pn2
R
2
0
2
Undefined
Pn1DR
R/W
Pn1
R
1
0
1
Undefined
Pn0DR
R/W
Pn0
R
0
0
0

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