DF61657CN35FTV Renesas Electronics America, DF61657CN35FTV Datasheet - Page 694

• Manufacturer Part Number: DF61657CN35FTV
• Description: IC H8SX/1657 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61657CN35FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 35MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 768KB (768K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: 3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 18 Flash Memory (0.18-µm F-ZTAT Version)
18.7.2
The programming/erasing interface parameters specify the operating frequency, storage place for
program data, start address of programming destination, and erase block number, and exchanges
the execution result. These parameters use the general registers of the CPU (ER0 and ER1) or the
on-chip RAM area. The initial values of programming/erasing interface parameters are undefined
at a power-on reset or a transition to software standby mode.
Since registers of the CPU except for ER0 and ER1 are saved in the stack area during download of
an on-chip program, initialization, programming, or erasing, allocate the stack area before
performing these operations (the maximum stack size is 128 bytes). The return value of the
processing result is written in R0. The programming/erasing interface parameters are used in
download control, initialization before programming or erasing, programming, and erasing. Table
18.4 shows the usable parameters and target modes. The meaning of the bits in the flash pass and
fail result parameter (FPFR) varies in initialization, programming, and erasure.
Table 18.4 Parameters and Target Modes
Note:
Download Control: The on-chip program is automatically downloaded by setting the SCO bit in
FCCS to 1. The on-chip RAM area to download the on-chip program is the 4-kbyte area starting
from the start address specified by FTDAR. Download is set by the programming/erasing interface
registers, and the download pass and fail result parameter (DPFR) indicates the return value.
Rev. 2.00 Jun. 28, 2007 Page 668 of 864
REJ09B0341-0200
Parameter
DPFR
FPFR
FPEFEQ
FMPAR
FMPDR
FEBS
*
Programming/Erasing Interface Parameters
A single byte of the start address of the on-chip RAM specified by FTDAR
Download
O
O




Initialization

O
O



Programming

O

O
O

Erasure

O



O
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial
Value
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Allocation
On-chip RAM*
R0L of CPU
ER0 of CPU
ER1 of CPU
ER0 of CPU
ER0 of CPU