DF61657CN35FTV Renesas Electronics America, DF61657CN35FTV Datasheet - Page 583

IC H8SX/1657 MCU FLASH 120TQFP

DF61657CN35FTV

Manufacturer Part Number
DF61657CN35FTV
Description
IC H8SX/1657 MCU FLASH 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of DF61657CN35FTV

Core Processor
H8SX
Core Size
32-Bit
Speed
35MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
82
Program Memory Size
768KB (768K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
For Use With
3DK1657 - DEV EVAL KIT FOR H8SX/1657
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
DF61657CN35FTV
Manufacturer:
RENESAS
Quantity:
101
Part Number:
DF61657CN35FTV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
14.3.5
SMR is used to set the SCI's serial transfer format and select the baud rate generator clock source.
Some bits in SMR have different functions in normal mode and smart card interface mode.
• When SMIF in SCMR = 0
• When SMIF in SCMR = 1
Bit Functions in Normal Serial Communication Interface Mode (When SMIF in SCMR = 0):
Bit
7
6
5
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Bit Name
C/A
CHR
PE
Serial Mode Register (SMR)
R/W
R/W
C/A
GM
7
0
7
0
Initial
Value
0
0
0
CHR
R/W
R/W
BLK
6
0
6
0
R/W
R/W
R/W
R/W
R/W
R/W
PE
PE
5
0
5
0
Description
Communication Mode
0: Asynchronous mode
1: Clocked synchronous mode
Character Length (valid only in asynchronous mode)
0: Selects 8 bits as the data length.
1: Selects 7 bits as the data length. LSB-first is fixed and
In clocked synchronous mode, a fixed data length of 8
bits is used.
Parity Enable (valid only in asynchronous mode)
When this bit is set to 1, the parity bit is added to transmit
data before transmission, and the parity bit is checked in
reception. For a multiprocessor format, parity bit addition
and checking are not performed regardless of the PE bit
setting.
the MSB (bit 7) in TDR is not transmitted in
transmission.
R/W
R/W
O/E
O/E
4
0
4
0
Section 14 Serial Communication Interface (SCI)
STOP
BCP1
R/W
R/W
3
0
3
0
Rev. 2.00 Jun. 28, 2007 Page 557 of 864
BCP0
R/W
R/W
MP
2
0
2
0
CKS1
CKS1
R/W
R/W
1
0
1
0
REJ09B0341-0200
CKS0
CKS0
R/W
R/W
0
0
0
0

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